Abstract: Based on the analysis of the relationship between the IA-D1 high-speed CCD device drive timing of DALSA, a drive timing generator with adjustable exposure time and high-speed camera is designed. Complex programmable logic device (CPLD) is selected as the hardware design platform, the drive timing generator is described in hardware using VHDL language, and the designed drive timing generator is functionally simulated using EDA software. It is adapted to the Lattice programmable logic device ISPLS15256. System test results show that the developed drive timing generator can not only meet the drive requirements of high-speed CCD cameras, but also adjust their exposure time.
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