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CY7C68013SLAVEFIFO interface program written in VerilogHDL

  • 2013-07-01
  • 657.05KB
  • Points it Requires : 1

Detailed description: CY7C68013 SLAVE FIFO interface program written in Verilog HDL, which is available for actual testing. It can be directly connected to the host computer to transmit data. File list: Synchronous FIFOIN test passed..................\\README.txt ..................\\Synchronous AUTOIN test description.pdf ..................\\Synchronous automatic input CPLD ..................\\................\\db ..................\\................\\..\\fifo_cntl.cbx.xml ..................\\Synchronous automatic input firmware..................\\................\\build.bat ..................\\................\\readme.txt

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