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Verilog Courseware

2020-08-29
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Design Example 1 • Describe the D flip-flop with gate-level structure: Design Example 2 • Construct a higher-level module from the designed modules Design Example 3 • Write a test module to check whether the design is correct through simulation: Verilog HDL Design Example 4 • Design of finite state machine - Finite state machine is a hardware sequential circuit composed of register group and combinational logic; - Its state (that is, the finite number of states composed of the combination of 1 and 0 states of the register group) can only be changed from one state to another under the same clock transition edge; - Which state it turns to depends not only on the input values, but also on the current state. - The state machine can be used to generate complex control logic that switches at the clock transition edge, which is the control core of digital logic. Complex control logic is the control core of digital logic. Design Example 4 (Continued)

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