Abstract How to assemble TCP/IP packets into data burst in OBS edge nodes is discussed. Min-burst-length-max-assembly-period algorithm is preferred and implemented on Xilinx® VirtexII Pro FPGA. A state machine controls the assembly process. Sharing buffer memory is proposed to save memory resources. That is, the number of physical burst queues is less than that of burst types since the inputs is random.Key words OBS; edge node; burst queue; sharing buffer memory
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