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AVS Adaptive Loop Filter Hardware Design

  • 2013-09-22
  • 256.32KB
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  An adaptive loop filter suitable for AVS is designed. Due to the high computational complexity, the hardware design of the adaptive loop filter is realized by parallel plus pipelining, which meets the requirements of real-time decoding. The design and simulation are carried out in Verilog language, and the FPGA-* certification is passed. The circuit scale is about 30,000 gates and the maximum frequency can reach 140MHz, which can decode 720p/1080i high-definition AVS code stream in real time.

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