In order to improve the real-time performance of Fast Fourier Transform (FFT) data processing, this paper uses the rich logic resources and fast operation speed of Field Programmable Array (FPGA) and the hierarchical characteristics of FFT algorithm to realize the pipeline working mode design of high-speed and high-order FFT. Through the design method introduced in this paper, a 1 024-point time-decimated FFT with an operating frequency of more than 50 MHz and data pipeline input and output is realized on Xilinx Virtex-II series FPGA.
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