pdf

A FPGA three-level interconnection network testing method based on matching theory

  • 2013-09-22
  • 312.83KB
  • Points it Requires : 2

This paper proposes a matching theory-based test method to reduce the number of configurations and is independent of the array size for testing interconnect networks containing three-level programmable switches in FPGAs. This method establishes a structural test graph, divides the graph into blocks according to the length of the paths, and applies the principles of minimum coverage and maximum matching to reduce the number of configurations. For different interconnect network structures, compared with other methods, this method reduces the number of configurations by at least 10%, and is independent of the array size.

unfold

You Might Like

Uploader
rubyonrails
 

Recommended ContentMore

Popular Components

Just Take a LookMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

About Us Customer Service Contact Information Datasheet Sitemap LatestNews


Room 1530, 15th Floor, Building B, No.18 Zhongguancun Street, Haidian District, Beijing, Postal Code: 100190 China Telephone: 008610 8235 0740

Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号
×