This paper proposes a matching theory-based test method to reduce the number of configurations and is independent of the array size for testing interconnect networks containing three-level programmable switches in FPGAs. This method establishes a structural test graph, divides the graph into blocks according to the length of the paths, and applies the principles of minimum coverage and maximum matching to reduce the number of configurations. For different interconnect network structures, compared with other methods, this method reduces the number of configurations by at least 10%, and is independent of the array size.
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