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Working Principle of Watchdog Timer

2013-09-20
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When enabled, the WDT will increment until it overflows, or “times out.” A WDT time-out forces a device reset, unless the device is in Sleep or Idle mode. To avoid a WDT time-out reset, the user must periodically clear the Watchdog Timer using the PWRSAV or CLRWDT instructions. If the WDT times out in Sleep or Idle mode, the device wakes up and continues code execution from the point where the PWRSAV instruction was executed. In both cases, the WDTO bit (RCON<4>) is set, indicating that the device Reset or wake-up event was caused by a WDT time-out. If the WDT wakes the CPU from Sleep or Idle mode, the Sleep status bit (RCON<3>) or Idle status bit (RCON<2>) is also set, indicating that the device was previously in a power-saving mode. 9.2.1 Enabling and Disabling the WDT The WDT can be enabled or disabled using the FWDTEN (CW1<7>) Configuration bit. When the FWDTEN Configuration bit is set, the WDT is enabled. This is the default value for an erased device. Refer to the device data sheet for more details on the Flash Configuration Word registers.

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