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Design of SDX bus and Wishbone bus interface based on FPGA

  • 2013-09-22
  • 681.58KB
  • Points it Requires : 2

This paper introduces the design and implementation of the SDX bus and Wishbone bus interface conversion based on the hardware description language Verilog HDL, and uses Modelsim to perform functional simulation, synthesizes on the QuartusⅡ software platform, and finally debugs on Altera\'s CycloneⅢ series FPGA. The experiment proves the feasibility of the design.

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