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Research on Turbo Code Encoding and Its FPGA Implementation

2014-03-05
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This paper takes the FPGA implementation of Turbo code decoder as the goal, and conducts in-depth research on the iterative decoding algorithm of Turbo code and its decoding algorithm implementation in hardware language. This paper first conducts in-depth research on the encoding and decoding principle of Turbo code in theory, and verifies and simulates its MAP decoding algorithm in C language. Then, the derivative algorithms of Turbo code MAP algorithm, namely LOG_MAP and MAX_LOG_MAP algorithms, are simulated and tested in C program. Subsequently, this paper also simulates and compares some parameters that have an important impact on MAP decoding performance in C program. Finally, considering the simplification of hardware implementation, MAX-Log-MAP algorithm becomes the hardware implementation scheme of this paper. This paper adopts modular design, and proposes some improved schemes based on the design of each module, improves the synchronization problem in the design of Turbo code encoder, and studies the hardware implementation of block parallel Turbo code decoding algorithm. In the design, the \"top-down\" and \"bottom-up\" design methods are comprehensively used. Through the functional module division, the system parameters are reasonably set, and the parameters are passed between modules, the Turbo code encoder has good flexibility.

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