Abstract: This application note describes how sampling clock jitter (time interval error or \"TIE jitter\") affects the performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) jitter tolerance in these devices. The article also provides an application example ofa simple highly jittered cycle-skipped sampling clock and describes a method for generating a properbroadband jittered clock. The document then goes on to compare Maxim\'s audio DAC jitter tolerance to competitor audio DACs. Maxim\'s exceptionally high jitter tolerance allows very simple and low-cost sampleclock implementations.
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