zip

FPGA Verification of a Complex Chip

  • 2013-09-22
  • 323.96KB
  • Points it Requires : 2

The module hierarchy construction algorithm and the improved KL algorithm are introduced to divide the design, which effectively reduces the number of interconnection signals between FPGAs. Through the pin multiplexing (CPM) method, the problem of insufficient pins caused by too many interconnections between multiple FPGAs is solved. On the other hand, the operating frequency of FPGA is much lower than the operating frequency of the actual chip. By setting the delay register in the interface and modifying the system software, the performance of the actual tape-out chip can be accurately evaluated, and the experimental error is within 2%.

unfold

You Might Like

Uploader
justyouandmehr
 

Recommended ContentMore

Popular Components

Just Take a LookMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

About Us Customer Service Contact Information Datasheet Sitemap LatestNews


Room 1530, 15th Floor, Building B, No.18 Zhongguancun Street, Haidian District, Beijing, Postal Code: 100190 China Telephone: 008610 8235 0740

Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号
×