The module hierarchy construction algorithm and the improved KL algorithm are introduced to divide the design, which effectively reduces the number of interconnection signals between FPGAs. Through the pin multiplexing (CPM) method, the problem of insufficient pins caused by too many interconnections between multiple FPGAs is solved. On the other hand, the operating frequency of FPGA is much lower than the operating frequency of the actual chip. By setting the delay register in the interface and modifying the system software, the performance of the actual tape-out chip can be accurately evaluated, and the experimental error is within 2%.
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