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Design simulation using ModelSim

  • 2013-09-22
  • 334.08KB
  • Points it Requires : 2

ModelSim is an HDL simulation tool. We can use this software to simulate the designed VHDL or Verilog program, and support various common IEEE hardware description language standards. Mixed simulation of two languages ​​can be performed, but it is recommended that you only simulate one language.

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