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Application of CPLD in Multi-channel High-speed Synchronous Data Acquisition System

  • 2013-09-18
  • 71.89KB
  • Points it Requires : 2

It is designed with VHDL language and uses CPLD to control the analog/digital conversion circuit to complete high-speed synchronous digital/analog conversion of multiple analog inputs, with fault tolerance and self-checking capabilities. A parallel interface is used between CPLD and the processor, which has good portability and reliability.

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