A master\'s degree thesis from Central China Normal University

Recommended ContentMore

Open source project More

• electronic clock
• Ultrasonic Sensing Subsystem Reference Design for Gas Flow Measurement
• [DIY Design] Based on HLW8032 electric energy metering system
• Gordian Knot
• [Tuya Smart] Thermohygrometer based on Tuya Smart
• Station B Environmental Monitoring 4.0
• Photoelectric sensor EE-SX1321
• MAXREFDES1169: ±15V/75mA and ±7.5V/75mA output, ISO-BUCK DC-DC power module
• Adapter board collection
• Sampling circuit schematic diagram

Searched by Users

• Download the Linux Common Command Set Detailed Explanation (CHM)
• Quick central control Think Control programming reference document
• STM32F103RBT6 minimum system
• Simulation Analysis of Three-phase Three-level VIENNA Rectifier
• STM32F3 and F4 series Cortex M4 core programming manual.pdf
• Advanced C++ Programming (3rd Edition).[US]Marc Gregoire (Detailed Bookmarks).pdf
• Introduction to Data Compression (4th Edition).pdf
• Samsung NAND Flash Memory Specification K9F4G08U0D
• TFT 2.4 inch LCD User Manual
• STM32 fatfs transplantation, support long file names, 8GSD card file reading and writing

Just Take a LookMore

• Questions about DDR3 VTT
  [i=s] This post was last edited by yshmily on 2019-4-7 21:18 [/i] I have come across 32-bit SOC with two 16-bit DDR3Ls, both of which use the VTT short-circuit method. However, I have come across two
• [Evaluation of Motor Kit P-NUCLEO-IHM]-3.2, Task Check-in (Advanced Tasks, Suggestions and Feedback)
  [i=s]This post was last edited by yang_alex on 2018-7-4 19:41[/i] [b][size=4]Advanced Task: Comparative Evaluation of New and Old Versions of Motor Driver Library[/size][/b] In general, in recent year
• Phase Noise Analysis of Phase-Locked Loop Frequency Synthesizer
  Abstract The phase noise of the frequency synthesizer directly affects the improvement factor of the moving target radar. This paper focuses on a comprehensive analysis of the phase noise of the phase
• EEWORLD University Hall----Live Replay: Keysight High-Speed Bus PCIe5.0 Technology Development and Test Sharing
  Live replay: Keysight high-speed bus PCIe5.0 technology development and test sharing : https://training.eeworld.com.cn/course/6168
• CMSIS_RTOS_Tutorial self-translated Chinese version
  [backcolor=white][color=#000000]I. Introduction[/color][/backcolor] [backcolor=white][color=#000000]This document is an excerpt from "The Designers Guide to the Cortex-M Processor Family" by Trevor Ma
• [Qinheng Trial] Run the ID reading routine
• Two 28335s are used simultaneously
• 【ufun learning】Part 2: Initial test demo example
• Problems with temperature acquisition based on stm32f446re
• Simple method of single chip microcomputer processing password

Trending Downloads

• Data structure C code implementation
• FDS6694
• A new passive soft-switching converter
• Application of Virtual Instrument in Frequency Parameter Measurement and Test
• AHCI Serial ATA Advanced Host Controller Interface
• Design of a special/general keyboard based on AT89C55 single chip microcomputer
• Import spice model method
• In C or C++ environment
• Multimedia editing software
• Source code for implementing fat32 system on blackfin platform

Trending ArticlesMore

• The promised AI chip has not been launched yet. What happened to Nervana, which was acquired by Intel?
• Is it feasible to export Gree chips?
• Lenovo Xiaoxin Pro 13 2019 Standard Pressure Ryzen Edition Thin and Light Laptop Review
• Super dry goods | PCIe 5.0 update and PCIe 6.0 outlook
• Transformation and "self-rescue": the life and death line of 600,000 offline education and training institutions
• Qi Lu, YC China's employee No. 01
• Case Study: Application of Doherty Power Amplifier Module in Large-Scale Antenna Array System
• Infected! The world's largest MLCC factory shuts down
• Stock Market News: SASAC urges central enterprises to innovate independently: overcome "bottleneck" problems in the field of core technologies!