This paper studies and implements a method to improve the HDLC (High Level Data Link Contr01) protocol. This method changes the traditional synchronous transmission mode of the HDLC protocol into an asynchronous transmission mode, which not only retains the main advantages of the original HDLC protocol, but also enhances the anti-interference performance of the transmission data and saves the synchronous clock interface connection of the communication system. This paper briefly introduces the HDLC protocol specification, and provides the VHDL code of CRC and the \"0\" deletion part. Finally, the asynchronous transmission mode of the HDLC protocol is described, and the improvement of the HDLC protocol is completed through FPGA.
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