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8086 bus operation, interrupt system and bus request

2013-09-22
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8086 bus operation: When the 8086 microprocessor transfers data with the off-chip memory or I/O interface, the bus operation specified by 8086 is executed through the BIU. Composition of the bus cycle: The basic bus cycle of 8086 is 4 clock cycles, and each clock cycle interval is called a T state. 8086 interrupt system: The 8086 microprocessor can handle 256 interrupts. 8086 response to external hardware interrupt request INTR: When INTR has a high level, there is a maskable interrupt request. If IF=1 at this time and the current instruction is executed, it enters the interrupt response cycle. The processing process is as follows: INTA# sends a valid signal in two bus cycles respectively. In the second cycle, 8086 reads the interrupt type code to protect the scene: the flag register is pushed into the stack, the IF and TF flags are cleared, and the breakpoint is protected (the next instruction address is pushed into the stack). 8086 bus request: In a system, if there are multiple master modules that can control the bus, the transfer of bus usage rights involves a request and response process.

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