Learning Development Board Schematic-Embedded Development-EEWORLD

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quartus18.1
Error (10054): Verilog HDL File I/O error at ROM.v(15): can't open Verilog Design File "rom_init.dat". Please help. What should I do if I encounter this problem? Reinstalling the software doesn't help
Why are there always connection points when drawing the wiring of the schematic in KICAD? And the lines are always misplaced. Why is this the case?
Is it because I adjusted the grid size?
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Learning Development Board Schematic

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