Embedded engineering based on ACTEL\'s Fusion series chips

Detailed description: Embedded project developed based on ACTEL Fusion series chips. I2C function is realized, including the written Core. The files include the project developed by Libero and the project developed by Keil. File listCoreI2C\\\\ACTL_Prj\\\\CortexM1\\\\constraint\\\\CortexM1_top.dtf\\\\core.ddf .......\\\\........\\\\........\\\\..........\\\\CortexM1_top.pdc .......\\\\........\\\\.....\\\\..reconsole\\\\common\\\\CoreAHB2APB\\\\CoreAHB2APB.cxf .......\\ \\.....\\\\........\\\\...........\\\\......\\\\.....\\\\rtl\\\\verilog\\\\o\\\\CoreAHB2APB.....\\\\........\\\\........\\\\.....\\\\......\\\\.....Lite\\\\CoreAHBLite.cxf .......\\\\.....\\\\........\\\\.....\\\\......\\\\.....\\\\coreparameters.v .......\\\\.... .\\\\.....\\\\.....\\\\......\\\\.....\\\\rtl\\\\verilog\\\\o\\\\CoreAHBLite.v .......\\\\........\\\\........\\\\...........\\\\......\\\\.....\\\\...\\\\.....\\\\.\\\\Decoder.v .......\\\\........\\\\........\\\\.....\\\\......\\\\.....\\\\...\\\\.......\\\\.\\\\DefaultSlave.....\\\\........\\\\........\\\\.....\\\\.....\\\\.....\\\\....\\\\.....\\ \\.\\\\MuxS2M.v .......\\\\........\\\\.....\\\\.....\\\\......\\\\.....PB\\\\CoreAPB.cxf .......\\\\........\\\\........\\\\.....\\\\......\\\\.....\\\\coreparameters.v .......\\\\........\\\\........\\\\.....\\\\......\\\\.......\\\\rtl\\\\verilog\\\\o\\\\CoreAPB. v .......\\\\........\\\\........\\\\...........\\\\......\\\\.....\\\\...\\\\.....\\\\.\\\\MuxP2B.v .......\\\\........\\\\........\\\\...........\\\\......\\\\....GPIO\\\\bfm\\\\CoreGPIO_scriptlet.bfm .......\\\\........\\\\........\\\\.....\\\\......\\\\........\\\\CoreGPIO.cxf .......\\\\.....\\\\........\\\\.....\\\\......\\\\........\\\\coreparameters.v .......\\\\.....\\ \\.....\\\\...........\\\\......\\\\........\\\\rtl\\\\verilog\\\\o\\\\CoreGPIO.....\\\\...........\\\\.....\\\\...........\\\\.OREI2C\\\\COREI2C.cxf .......\\\\........\\\\.....\\\\...........\\\\......\\\\.....\\\\coreparameters.v .......\\\\........\\\\.....\\\\ ...........\\\\......\\\\.....\\\\mti\\\\lib_vlog_obs\\\\COREI2C_LIB\\\\_info .......\\\\........\\\\........\\\\..........\\\\......\\\\.....\\\\...\\\\scripts\\\\wavetb_vlog.do .......\\\\........\\\\........\\\\.....\\\\......\\\\.....\\\\rtl\\\\vlog\\\\core_obfuscated\\\\corei2c.v .......\\\\........\\\\........\\\\.....\\\\......\\\\.....\\\\....\\\\....\\ \\..................\\\\corei2creal.v .......\\\\.....\\\\.....\\\\.....\\\\....\\\\.....\\\\....\\\\....\\\\test\\\\user\\\\smbus_wrp.v .......\\\\.....\\\\.....\\\\.....\\\\....\\\\.....\\\\....\\\\....\\\\....\\\\....\\\\testbench.v .......\\\\.....\\\\.....\\\\.....\\\\.... \\\\.oreInterrupt\\\\bfm\\\\CoreInterrupt_scriptlet.bfm .......\\\\........\\\\........\\\\...........\\\\......\\\\.............\\\\CoreInterrupt.cxf .......\\\\........\\\\........\\\\........\\\\......\\\\.....\\\\coreparameters.v .......\\\\........\\\\........\\\\.....\\\\......\\\\.....\\\\rtl\\\\verilog\\\\o\\\\CoreInterrupt.v .......\\\\......\\\\ ........\\\\..........\\\\......\\\\....MemCtrl\\\\bfm\\\\CoreMemCtrl_scriptlet.bfm .......\\\\........\\\\........\\\\........\\\\......\\\\...........\\\\CoreMemCtrl.cxf .......\\\\.....\\\\...........\\\\.....\\\\......\\\\.....\\\\coreparameters.v .......\\\\..........\\\\. .......\\\\..........\\\\......\\\\.....\\\\rtl\\\\verilog\\\\o\\\\CoreMemCtrl.v .......\\\\........\\\\........\\\\...........\\\\......\\\\....Remap\\\\bfm\\\\CoreRemap_scriptlet.bfm

.......\\\\........\\\\........\\\\...........\\\\......\\\\.........\\\\CoreRemap.cxf

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.......\\\\........\\\\........\\\\...........\\\\......\\\\....UARTapb\\\\coreparameters.v

.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\CoreUARTapb.cxf

.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\mti\\\\lib_vlog_obs\\\\COREUARTAPB_LIB\\\\@c@o@r@e@u@a@r@t\\\\verilog.psm

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.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\...\\\\............\\\\...............\\\\..lock_gen\\\\verilog.psm

.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\...\\\\............\\\\...............\\\\..........\\\\_primary.dat

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.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\...\\\\............\\\\...............\\\\.........\\\\_primary.dat

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.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\...\\\\............\\\\...............\\\\testbnch\\\\verilog.psm

.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\...\\\\............\\\\...............\\\\........\\\\_primary.dat

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.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\...\\\\............\\\\...............\\\\_info

.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\...\\\\scripts\\\\wave_vlog.do

.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\rtl\\\\vlog\\\\amba_obfuscated\\\\Clock_gen.v

.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\...\\\\....\\\\...............\\\\CoreUART.v

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.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\...\\\\....\\\\...............\\\\fifo_256x8_fusion.v

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.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\...\\\\....\\\\test\\\\amba\\\\testbnch.v

.......\\\\........\\\\........\\\\...........\\\\......\\\\...texM1Top\\\\bfm\\\\subsystem.bfm

.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\coreparameters.v

.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\CortexM1Integration\\\\bfm\\\\compiler\\\\bfmCompile.tcl

.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\...................\\\\...\\\\rtl\\\\verilog\\\\o\\\\AhbLiteBridge.v

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.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\...................\\\\M1AFS600-2\\\\0ki_0kd_1int_sm_debug\\\\layout\\\\arm_designer.cdb

.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\...................\\\\..........\\\\.....................\\\\timingshell\\\\verilog\\\\arm_precision.v

.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\...................\\\\..........\\\\.....................\\\\...........\\\\.......\\\\arm_synplify.v

.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\CortexM1Top.cxf

.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\rtl\\\\verilog\\\\o\\\\CortexM1Top.v

.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\...\\\\.......\\\\.\\\\ResetSync.v

.......\\\\........\\\\........\\\\...........\\\\......\\\\...........\\\\...\\\\.......\\\\.\\\\uj_jtag.v

.......\\\\........\\\\........\\\\...........\\\\CortexM1\\\\CoreAHB2APB_00\\\\CoreAHB2APB_00.xml

.......\\\\........\\\\........\\\\...........\\\\........\\\\.......Lite_00\\\\CoreAHBLite_00.xml

.......\\\\........\\\\........\\\\...........\\\\........\\\\.....PB_00\\\\CoreAPB_00.xml

.......\\\\........\\\\........\\\\...........\\\\........\\\\....GPIO_00\\\\CoreGPIO_00.xml

.......\\\\........\\\\........\\\\...........\\\\........\\\\....I2C_00\\\\CoreI2C_00.xml

.......\\\\........\\\\........\\\\...........\\\\........\\\\.....nterrupt_00\\\\CoreInterrupt_00.xml

.......\\\\........\\\\........\\\\...........\\\\........\\\\....MemCtrl_00\\\\CoreMemCtrl_00.xml

.......\\\\........\\\\........\\\\...........\\\\........\\\\....Remap_00\\\\CoreRemap_00.xml

.......\\\\........\\\\........\\\\...........\\\\........\\\\....UARTapb_00\\\\CoreUARTapb_00.xml

.......\\\\........\\\\........\\\\...........\\\\........\\\\CortexM1.cci

.......\\\\........\\\\........\\\\...........\\\\........\\\\cortexm1.cco