NE5517, NE5517A, AU5517
Dual Operational
Transconductance Amplifier
The AU5517 and NE5517 contain two current-controlled
transconductance amplifiers, each with a differential input and
push-pull output. The AU5517/NE5517 offers significant design and
performance advantages over similar devices for all types of
programmable gain applications. Circuit performance is enhanced
through the use of linearizing diodes at the inputs which enable a
10 dB signal-to-noise improvement referenced to 0.5% THD. The
AU5517/NE5517 is suited for a wide variety of industrial and
consumer applications.
Constant impedance of the buffers on the chip allow general use of
the AU5517/NE5517. These buffers are made of Darlington
transistors and a biasing network that virtually eliminate the change of
offset voltage due to a burst in the bias current I
ABC
, hence eliminating
the audible noise that could otherwise be heard in high quality audio
applications.
Features
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MARKING
DIAGRAMS
1
SOIC−16
D SUFFIX
CASE 751B
xx5517DG
AWLYWW
1
•
•
•
•
•
•
•
•
•
•
•
•
Constant Impedance Buffers
DV
BE
of Buffer is Constant with Amplifier I
BIAS
Change
Excellent Matching Between Amplifiers
Linearizing Diodes
High Output Signal-to-Noise Ratio
Pb−Free Packages are Available*
1
PDIP−16
N SUFFIX
CASE 648
NE5517yy
AWLYYWWG
1
Applications
Multiplexers
Timers
Electronic Music Synthesizers
Dolby® HX Systems
Current-Controlled Amplifiers, Filters
Current-Controlled Oscillators, Impedances
xx
yy
A
WL
YY, Y
WW
G
= AU or NE
= AN or N
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
N, D Packages
I
ABCa
1
D
a
2
+IN
a
3
−IN
a
4
VO
a
5
V− 6
IN
BUFFERa
7
VO
BUFFERa
8
16
15
14
13
12
11
10
9
I
ABCb
D
b
+IN
b
−IN
b
VO
b
V+
IN
BUFFERb
VO
BUFFERb
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2013
June, 2013
−
Rev. 4
1
Publication Order Number:
NE5517/D
NE5517, NE5517A, AU5517
PIN DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
I
ABCa
D
a
+IN
a
−IN
a
VO
a
V−
IN
BUFFERa
VO
BUFFERa
VO
BUFFERb
IN
BUFFERb
V+
VO
b
−IN
b
+IN
b
D
b
I
ABCb
Amplifier Bias Input A
Diode Bias A
Non-inverted Input A
Inverted Input A
Output A
Negative Supply
Buffer Input A
Buffer Output A
Buffer Output B
Buffer Input B
Positive Supply
Output B
Inverted Input B
Non-inverted Input B
Diode Bias B
Amplifier Bias Input B
Description
V+
11
D4
Q6
Q10
D6
Q14
7,10
Q12
Q13
8,9
Q7
Q11
2,15
D2
−INPUT
4,13
1,16
AMP BIAS
INPUT
Q1
D1
V−
6
Q4
Q5
D3
+INPUT
3,14
VOUTPUT
5,12
Q15
Q2
Q9
R1
Q8
D5
D8
Q16
D7
Q3
Figure 1. Circuit Schematic
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2
NE5517, NE5517A, AU5517
B
AMP
BIAS
INPUT
16
B
DIODE
BIAS
15
B
INPUT
(+)
14
B
INPUT
(−)
13
B
OUTPUT
12
B
BUFFER
INPUT
10
B
BUFFER
OUTPUT
9
V+ (1)
11
−
B
+
+
A
−
1
AMP
BIAS
INPUT
A
2
DIODE
BIAS
A
3
INPUT
(+)
A
4
INPUT
(−)
A
5
OUTPUT
A
6
V−
7
BUFFER
INPUT
A
8
BUFFER
OUTPUT
A
NOTE:
V+ of output buffers and amplifiers are internally connected.
Figure 2. Connection Diagram
MAXIMUM RATINGS
Rating
Supply Voltage (Note 1)
Power Dissipation, T
amb
= 25
°C
(Still Air) (Note 2)
NE5517N, NE5517AN
NE5517D, AU5517D
Thermal Resistance, Junction−to−Ambient
D Package
N Package
Differential Input Voltage
Diode Bias Current
Amplifier Bias Current
Output Short-Circuit Duration
Buffer Output Current (Note 3)
Operating Temperature Range
NE5517N, NE5517AN
AU5517T
Operating Junction Temperature
DC Input Voltage
Storage Temperature Range
Lead Soldering Temperature (10 sec max)
Symbol
V
S
P
D
Value
44 V
DC
or
±22
1500
1125
140
94
±5.0
2.0
2.0
Indefinite
20
0
°C
to +70
°C
−40
°C
to +125
°C
150
+V
S
to
−V
S
−65
°C
to +150
°C
230
°C
°C
mA
°C
Unit
V
mW
R
qJA
°C/W
V
IN
I
D
I
ABC
I
SC
I
OUT
T
amb
V
mA
mA
T
J
V
DC
T
stg
T
sld
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. For selections to a supply voltage above
±22
V, contact factory.
2. The following derating factors should be applied above 25
°C
N package at 10.6 mW/°C
D package at 7.1 mW/°C.
3. Buffer output current should be limited so as to not exceed package dissipation.
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3
NE5517, NE5517A, AU5517
ELECTRICAL CHARACTERISTICS
(Note 4)
AU5517/NE5517
Characteristic
Input Offset Voltage
Test Conditions
Overtemperature Range
I
ABC
5.0
mA
Avg. TC of Input Offset Voltage
Diode Bias Current
(I
D
) = 500
mA
5.0
mA
≤
I
ABC
≤
500
mA
Avg. TC of Input Offset Current
Overtemperature Range
Avg. TC of Input Current
Overtemperature Range
g
M
6700
5400
I
BIAS
V
OS
I
OS
Symbol
V
OS
Min
Typ
0.4
0.3
7.0
0.5
0.1
0.1
0.001
0.4
1.0
0.01
9600
0.3
R
L
= 0, I
ABC
= 5.0
mA
R
L
= 0, I
ABC
= 500
mA
R
L
= 0, Overtemperature
Range
R
L
=
∞,
5.0
mA
≤
I
ABC
≤
500
mA
R
L
=
∞,
5.0
mA
≤
I
ABC
≤
500
mA
I
ABC
= 500
mA,
both channels
D
V
OS
/D V+
D
V
OS
/D V−
CMRR
80
±12
Referred to Input (Note 5)
20 Hz < f < 20 kHz
I
ABC
= 0, Input =
±4.0
V
I
ABC
= 0 (Refer to Test Circuit)
R
IN
B
W
Unity Gain Compensated
5
5
Refer to Buffer V
BE
Test
Circuit (Note 6)
SR
IN
BUFFER
VO
BUFFER
10
0.5
5.0
10
I
IN
I
OUT
350
300
5.0
500
650
3.0
350
300
13000
7700
4000
5.0
8.0
0.6
5
Max
5.0
5.0
Min
NE5517A
Typ
0.4
0.3
7.0
0.5
0.1
0.1
0.001
0.4
1.0
0.01
9600
0.3
5.0
500
7.0
650
12000
5.0
7.0
2.0
3.0
0.6
Max
2.0
5.0
2.0
Unit
mV
DV
OS
/DT
V
OS
Including Diodes
Input Offset Change
Input Offset Current
DI
OS
/DT
Input Bias Current
DI
B
/DT
Forward Transconductance
g
M
Tracking
Peak Output Current
mV/°C
mV
mV
mA
mA/°C
mA
mA/°C
mmho
dB
mA
Peak Output Voltage
Positive
Negative
Supply Current
V
OS
Sensitivity
Positive
Negative
V
OUT
+12
−12
+14.2
−14.4
2.6
20
20
110
±13.5
100
0.02
0.2
26
2.0
50
0.4
5.0
100
100
4.0
150
150
+12
−12
+14.2
−14.4
2.6
20
20
4.0
150
150
V
I
CC
mA
mV/V
Common-mode Rejection
Ration
Common-mode Range
Crosstalk
Differential Input Current
Leakage Current
Input Resistance
Open-loop Bandwidth
Slew Rate
Buffer Input Current
Peak Buffer Output Voltage
DV
BE
of Buffer
80
±12
110
±13.5
100
0.02
0.2
10
5.0
dB
V
dB
nA
nA
kW
MHz
V/ms
5.0
mA
V
mV
10
26
2.0
50
0.4
10
0.5
5.0
4. These specifications apply for V
S
=
±15
V, T
amb
= 25°C, amplifier bias current (I
ABC
) = 500
mA,
Pins 2 and 15 open unless otherwise
specified. The inputs to the buffers are grounded and outputs are open.
5. These specifications apply for V
S
=
±15
V, I
ABC
= 500
mA,
R
OUT
= 5.0 kW connected from the buffer output to
−V
S
and the input of the buffer
is connected to the transconductance amplifier output.
6. V
S
=
±15,
R
OUT
= 5.0 kW connected from Buffer output to
−V
S
and 5.0
mA
≤
I
ABC
≤
500
mA.
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4
NE5517, NE5517A, AU5517
TYPICAL PERFORMANCE CHARACTERISTICS
10 3
INPUT OFFSET CURRENT (nA)
V
S
=
±15V
+125°C
-55°C
+25°C
5
4
INPUT OFFSET VOLTAGE (mV)
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
0.1mA
1mA
10mA
100mA
1000mA
10 4
V
S
=
±15V
V
S
=
±15V
INPUT BIAS CURRENT (nA)
10
3
10
2
-55°C
+125°C
10
+25°C
+125°C
10
2
-55°C
1
10
+25°C
+125°C
0.1
0.1mA
1mA
10mA
100mA
1000mA
AMPLIFIER BIAS CURRENT (I
ABC
)
AMPLIFIER BIAS CURRENT (I
ABC
)
1
0.1mA
1mA
10mA
100mA
1000mA
AMPLIFIER BIAS CURRENT (I
ABC
)
Figure 3. Input Offset Voltage
10 4
PEAK OUTPUT CURRENT (
μ
A)
V
S
=
±15V
+125°C
Figure 4. Input Bias Current
5
4
PEAK OUTPUT VOLTAGE AND
COMMON-MODE RANGE (V)
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
V
OUT
V
CMR
10 5
V
OUT
LEAKAGE CURRENT (pA)
V
CMR
V
S
=
±15V
RLOAD =
∞
T
amb
= 25°C
Figure 5. Input Bias Current
(+)V
IN
= (−)V
IN
= V
OUT
= 36V
10 4
10 3
+25°C
10 2
-55°C
10 3
0V
10 2
10
1
0.1mA
1mA
10mA
100mA
1000mA
0.1mA
1mA
10mA
100mA
1000mA
10
-50°C -25°C
0°C 25°C 50°C 75°C100°C125°C
AMPLIFIER BIAS CURRENT (I
ABC
)
AMPLIFIER BIAS CURRENT (I
ABC
)
AMBIENT TEMPERATURE (T
A
)
Figure 6. Peak Output Current
Figure 7. Peak Output Voltage and
Common-Mode Range
10 5
gM
10 4
mq
m
M
10 2
INPUT RESISTANCE (MEG
Ω
)
Figure 8. Leakage Current
TRANSCONDUCTANCE (gM) — (
μ
ohm)
10 4
INPUT LEAKAGE CURRENT (pA)
+125°C
PINS 2, 15
OPEN
V
S
=
±15V
PINS 2, 15
OPEN
10
1
10 3
10 2
+25°C
10 3
-55°C
+125°C
1
10
10 2
+25°C
0.1
1
10
0
1
2
3
4
5
6
INPUT DIFFERENTIAL VOLTAGE
7
0.1mA
1mA
10mA
100mA
1000mA
0.01
0.1mA
1mA
10mA
100mA
1000mA
AMPLIFIER BIAS CURRENT (I
ABC
)
AMPLIFIER BIAS CURRENT (I
ABC
)
Figure 9. Input Leakage
Figure 10. Transconductance
Figure 11. Input Resistance
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Analogue and Mixed Signal
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