ATSAML21E17B-MUT datasheet, PDF

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ATSAML21E17B-MUT: DescriptionMultilayer Ceramic Capacitors MLCC - SMD/SMT 0603 10uF 6.3volts X5R 20%; Categorysemiconductor The embedded processor and controller; File Size2MB，41 Pages; ManufacturerAtmel (Microchip)

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ATSAML21E17B-MUT Overview

Multilayer Ceramic Capacitors MLCC - SMD/SMT 0603 10uF 6.3volts X5R 20%

ATSAML21E17B-MUT Parametric

Parameter Name	Attribute value
Product Category	ARM Microcontrollers - MCU
Manufacturer	Atmel (Microchip)
RoHS	Details
Mounting Style	SMD/SMT
Package / Case	QFN-32
Core	ARM Cortex M0+
Data Bus Width	32 bit
Maximum Clock Frequency	48 MHz
Program Memory Size	128 kB
Data RAM Size	16 kB
ADC Resolution	12 bit
Operating Supply Voltage	3.3 V
Maximum Operating Temperature	+ 85 C
Packaging	Reel
Packaging	MouseReel
Packaging	Cut Tape
Analog Supply Voltage	3.3 V
DAC Resolution	12 bit
Data RAM Type	SRAM
I/O Voltage	3.3 V
Interface Type	I2C, LIN, SPI, USART, USB
Minimum Operating Temperature	- 40 C
Moisture Sensitive	Yes
Number of ADC Channels	10 Channel
Number of I/Os	25 I/O
Number of Timers/Counters	6 x 16 bit
Product	MCU
Program Memory Type	Flash
Factory Pack Quantity	5000
Supply Voltage - Max	3.63 V
Supply Voltage - Min	1.62 V
Watchdog Timers	Watchdog Timer
Unit Weight	0.006653 oz

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SMART ARM-based Microcontroller

SAM L21E / SAM L21G / SAM L21J Summary

DATASHEET SUMMARY

Introduction

Atmel | SMART SAM L21 is a series of Ultra low-power microcontrollers

using the 32-bit ARM Cortex -M0+ processor at max. 48MHz (2.46

CoreMark /MHz) and up to 256KB Flash and 40KB of SRAM in a 32, 48,

and 64 pin package. The sophisticated power management technologies,

such as power domain gating, SleepWalking, Ultra low-power peripherals

and more, allow for very low current consumptions. The highly configurable

peripherals include a touch controller supporting capacitive interfaces with

proximity sensing.

Features

•

Processor

–

ARM Cortex-M0+ CPU running at up to 48MHz

• Single-cycle hardware multiplier

• Micro Trace Buffer

Memories

–

32/64/128/256KB in-system self-programmable Flash

–

1/2/4/8KB Flash Read-While-Write section

–

4/8/16/32KB SRAM Main Memory

–

2/4/8/8KB SRAM Low power Memory

System

–

Power-on reset (POR) and brown-out detection (BOD)

–

Internal and external clock options

–

External Interrupt Controller (EIC)

–

16 external interrupts

–

One non-maskable interrupt

–

Two-pin Serial Wire Debug (SWD) programming, test and

debugging interface

Low Power

–

Idle, Standby, Backup, and Off sleep modes

–

SleepWalking peripherals

•

This is a summary document. A

complete document is available

on our Web site at

www.atmel.com

•

Atmel-42385J-SAM L21_Datasheet_Summary-06/2016

Table of Contents

Introduction......................................................................................................................1

1. Description.................................................................................................................5

Features.......................................................................................................................... 1

2. Configuration Summary............................................................................................. 7

3. Ordering Information................................................................................................10

3.1.

3.2.

3.3.

3.4.

SAM L21J...................................................................................................................................10

SAM L21G.................................................................................................................................. 11

SAM L21E...................................................................................................................................11

Device Identification....................................................................................................................11

4. Block Diagram......................................................................................................... 13

5. Pinout.......................................................................................................................15

5.1.

5.2.

5.3.

5.4.

SAM L21J...................................................................................................................................15

SAM L21J WLCSP64................................................................................................................. 16

SAM L21G..................................................................................................................................17

SAM L21E.................................................................................................................................. 18

6. Product Mapping......................................................................................................19

7. Processor and Architecture..................................................................................... 20

7.1.

7.2.

7.3.

7.4.

Cortex M0+ Processor................................................................................................................20

Nested Vector Interrupt Controller..............................................................................................21

Micro Trace Buffer...................................................................................................................... 23

High-Speed Bus System............................................................................................................ 24

8. Packaging Information............................................................................................. 29

8.1.

8.2.

8.3.

Thermal Considerations............................................................................................................. 29

Package Drawings......................................................................................................................30

Soldering Profile......................................................................................................................... 39

Atmel SAM L21E / SAM L21G / SAM L21J Summary [DATASHEET]

Atmel-42385J-SAM L21_Datasheet_Summary-06/2016

Description

Atmel | SMART SAM L21 is a series of Ultra low-power microcontrollers using the 32-bit ARM Cortex -

M0+ processor, and ranging from 32- to 64-pins with up to 256KB Flash and 40KB of SRAM. The SAM

L21 devices operate at a maximum frequency of 48MHz and reach 2.46 CoreMark /MHz. They are

designed for simple and intuitive migration with identical peripheral modules, hex compatible code,

identical linear address map and pin compatible migration paths between all devices in the product

series. All devices include intelligent and flexible peripherals, Atmel Event System for inter-peripheral

signaling, and support for capacitive touch button, slider and wheel user interfaces.

The Atmel SAM L21 devices provide the following features: In-system programmable Flash, 16-channel

direct memory access (DMA) controller, 12-channel Event System, programmable interrupt controller, up

to 51 programmable I/O pins, 32-bit real-time clock and calendar, up to five 16-bit Timer/Counters (TC)

and three Timer/Counters for Control (TCC) where each TC/TCC can be configured to perform frequency

and waveform generation, accurate program execution timing or input capture with time and frequency

measurement of digital signals. The TCs can operate in 8- or 16-bit mode, selected TCs can be cascaded

to form a 32-bit TC, and three timer/counters have extended functions optimized for motor, lighting and

other control applications. Two TCC can operate in 24-bit mode, the third TCC can operate in 16-bit

mode. The series provide one full-speed USB 2.0 embedded host and device interface; up to six Serial

Communication Modules (SERCOM) that each can be configured to act as an USART, UART, SPI, I

C up

to 3.4MHz, SMBus, PMBus, and LIN slave; up to twenty channel 1MSPS 12-bit ADC with programmable

gain and optional oversampling and decimation supporting up to 16-bit resolution, two 12-bit 1MSPS

DACs, two analog comparators with window mode, three independent cascadable OPAMPs supporting

internal connection with others analog features, Peripheral Touch Controller supporting up to 192 buttons,

sliders, wheels and proximity sensing; programmable Watchdog Timer, brown-out detector and power-on

reset and two-pin Serial Wire Debug (SWD) program and debug interface.

All devices have accurate and low-power external and internal oscillators. All oscillators can be used as a

source for the system clock. Different clock domains can be independently configured to run at different

frequencies, enabling power saving by running each peripheral at its optimal clock frequency, and thus

maintaining a high CPU frequency while reducing power consumption.

The SAM L21 devices have four software-selectable sleep modes, idle, standby, backup and off. In idle

mode the CPU is stopped while all other functions can be kept running. In standby all clocks and

functions are stopped except those selected to continue running. In this mode all RAMs and logic

contents are retained. The device supports SleepWalking. This feature allows the peripheral to wake up

from sleep based on predefined conditions, and thus allows some internal operation like DMA transfer

and/or the CPU to wake up only when needed, e.g. when a threshold is crossed or a result is ready. The

Event System supports synchronous and asynchronous events, allowing peripherals to receive, react to

and send events even in standby mode.

The SAM L21 devices have two software-selectable performance levels (PL0 and PL2) allowing the user

to scale the lowest core voltage level that will support the operating frequency. To further minimize

consumption, specifically leakage dissipation, the SAM L21 devices utilizes power domain gating

technique with retention to turn off some logic area while keeping its logic state. This technique is fully

handled by hardware.

The Flash program memory can be reprogrammed in-system through the SWD interface. The same

interface can be used for nonintrusive on-chip debugging of application code. A boot loader running in the

device can use any communication interface to download and upgrade the application program in the

Flash memory.

Atmel SAM L21E / SAM L21G / SAM L21J Summary [DATASHEET]

Atmel-42385J-SAM L21_Datasheet_Summary-06/2016

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