UBSC/ULSC – 60
+
GHz Ultra Broadband
Silicon Capacitors – Surface Mounted
Rev 2.5
Key Features
Ultra broadband performance up to 60
+
GHz
Resonance free
Phase stability
Ultra high stability of capacitance value over:
-
Temperature <
±
0.5 % (-55°C to +150°C)
- Voltage < 0.1 %/V
- Aging < 0.001 %/1000 hours
Key Applications
Optoelectronics/high-speed data
Trans-Impedance Amplifiers (TIA)
Receive-and-Transmit Optical Sub-Assembly
(ROSA/TOSA)
Synchronous Optical Networking (SONET)
High speed digital logic
Broadband test equipment
Broadband microwave/millimeter wave
Replacement of X7R and NP0
Low profile applications (400 or 100 µm)
Low ESL
High reliability (FIT < 0.017 parts/billion hours)
Compatible with lead free reflow-soldering*
* Please refer to our Assembly Application Note for more details
UBSC/ULSC Capacitors target
optical
communication systems
(ROSA/TOSA, SONET
and all optoelectronics) as well as
high speed
data systems
or products. The UBSC/ULSC are
designed for DC blocking, feedback, coupling and
bypass grounding applications. The unique
technology of integrated passive devices in silicon
developed by IPDiA, offers
low insertion loss,
low reflection and high phase stability
from 16
kHz up to 60 GHz for the UBSC and up to 20 GHz
for the ULSC. These deep trench silicon
capacitors have been developed with a
semiconductor MOS process.
The UBSC / ULSC capacitors provide
very high
reliability
and capacitance stability over
temperature (±0.5 %) and voltage. They have an
extended operating temperature range from -55 to
150°C.
Reliable and repeatable performances
are obtained thanks to a fully controlled
production line with high temperature curing
(above 900°C) generating a highly pure oxide.
The UBSC / ULSC series are compliant with
standard JEDEC assembly rules, making the
product fully compatible with high speed
automated pick-and-place manufacturing
operations. Case sizes of 0201 and 0603 are also
available. These capacitors are RoHS-compliant
and are available with ENIG terminations.
IPDiA Capacitors – UBSC/ULSC Series
Electrical Specifications
Part number
UBSC.xxx
935 151 423 510
935 151 723 510
935 152 423 510
935 152 723 510
935 151 424 610
935 152 424 610
935 151 425 610
935 152 425 610
ULSC.xxx
Product description
Surface Mount Ultra Broad Band Silicon Capacitor
from -55 to 150°C, 60
+
GHz with ENIG termination
Ultra Broadband Si Cap 10nF 60+GHz 400µm, BV>11V
Ultra Broadband Si Cap 10nF 60+GHz 400µm, BV>30V
Ultra Broadband Si Cap 10nF 60+GHz 100µm, BV>11V
Ultra Broadband Si Cap 10nF 60+GHz 100µm, BV>30V
Ultra Broadband Si Cap 100nF 60+GHz 400µm, BV>11V
Ultra Broadband Si Cap 100nF 60+GHz 100µm, BV>11V
Ultra Broadband Si Cap 100nF 60+GHz 400µm, BV>11V
Ultra Broadband Si Cap 100nF 60+GHz 100µm, BV>11V
Surface Mount Ultra Broad Band Silicon Capacitor
from -55 to 150°C, 20 GHz with ENIG termination
0402
0402
400µm
100µm
Case Size Thickness
Parameters
Capacitance range
Capacitance tolerance
Operating temperature range
Storage temperature
Temperature coefficient
Breakdown voltage (BV)
Capacitance variation
versus RVDC
Equivalent Serial Inductance
(ESL)
Equivalent Serial Resistance
(ESR)
Insulation resistance
Aging
Reliability
Capacitor height
(**) Other values on request.
(***) e.g. 100nF/0402/BV 11V
Value
10nF to 100 nF
(**)
±
15 %
(**)
-55 °C to 150 °C
- 70 °C to 165 °C
<±0.5 %, from -55 °C to +150 °C
11, 30 V
(**)
0.1 %/V (from 0 V to RVDC)
Max 100 pH
(***)
Max 400 m
(***)
100 G
min @ RVDC & +25°C
Negligible, < 0.001 % / 1000h
FIT<0.017 parts / billion hours
Max 400 µm or 100 µm
0201
0201
0201
0201
0402
0402
0603
0603
400µm
400µm
100µm
100µm
400µm
100µm
400µm
100µm
935 155 424 610 Ultra Broadband Si Cap 100nF 20 GHz 400µm, BV>11V
935 156 424 610 Ultra Broadband Si Cap 100nF 20 GHz 100µm, BV>11V
25°C
Fig.1: Capacitance variation vs temperature
(for UBSC and MLCC technologies)
Fig.2: Capacitance variation vs DC biasing
voltage (for UBSC and MLCC technologies)
Fig.3: 100 nF/0402 UBSC measurement results
(S-parameters in transmission mode)
UBSC/ULSC Capacitance Range
Available parts – see table above
For other values, contact your IPDiA sales representative
Termination and Outline
Termination
Lead-free nickel/solder coating compatible
with automatic soldering technologies:
reflow and manual.
Package Outline
For landing pad dimensions on your PCB layout, please refer
to IPDiA assembly application note.
W
( mm )
0201
0402
0603
Pad dimensions
a
0.15
0.30
0.40
b
0.40
0.50
0.90
c
0.30
0.40
0.80
Case size (typ. ±0.01mm)
L
0.80
1.20
1.80
W
0.60
0.70
1.10
T
0.40 (standard
profile) or 0.10
(low profile)
L
c
a
T
b
Packaging
Tape and reel, waffle pack, film frame carrier or raw wafer delivery.
Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner. The information
presented in this document does not form part of any
quotation or contract, is believed to be accurate and reliable
and may be changed without notice. No liability will be
accepted by the publisher for any consequence of its use.
Publication thereof does not convey nor imply any license
For more information, please visit:
http://www.ipdia.com
To contact us, email to:
sales@ipdia.com
Date of release: May 13th 2015
Document identifier: CL
Rev 2.0
UBSC/ULSC IPDiA Capacitors - 100µm - NiAu finishing
Assembly by Soldering
Table of Contents
Table of Contents .............................................................................................................................1
Introduction .......................................................................................................................................2
Handling precautions and storage ....................................................................................................2
Pad opening ......................................................................................................................................3
Process Flow ....................................................................................................................................3
Solder print material and stencil printing recommendations.............................................................5
Pick and Place ..................................................................................................................................7
Reflow soldering ...............................................................................................................................7
Revision ............................................................................................................................................8
Rev1.0
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UBSC/ULSC IPDiA Capacitors - 100µm - NiAu finishing
Assembly by Soldering
Introduction
This document describes the attachment techniques recommended by IPDiA for their
UBSC/ULSCC (100µm thickness) silicon capacitors on the customer substrates. This document
is non-exhaustive. Customers with specific attachment requirements or attachment scenarios that
are not covered by this document should contact IPDiA. The solder printing is described in this
document but other processes like solder jetting, capacitors pre-bumped, … can also be used
with the same recommendations.
IPDiA Silicon capacitor
(1206)
The silicon capacitor
mounted on PCB board
Handling precautions and storage
Silicon die must always be handled in a clean room environment (usually class 1000 (ISO 6)) but
the assembled devices don’t need to be handled in such an environment as the product is
already well packed. The remaining quantities have to be repacked immediately after any process
step, in the same conditions as before the opening (ESD bag + N2)
Store the capacitors in the manufacturer's package in the following conditions without a rapid
thermal change in an indoor room:
• Temperature: -10 to 40 degree C
• Humidity: 30 to 70%RH
Avoid storing the capacitors in the following conditions:
(a) Ambient air containing corrosive gas. (Chlorine, Hydrogen sulfide, Ammonia, Sulfuric
acid, Nitric oxide, etc.)
(b) Ambient air containing volatile or combustible gas
(c) In environments with a high concentration of airborne particles
(d) In liquid (water, oil, chemical solution, organic solvents, etc.)
(e) In direct sunlight
(f) In freezing environments
To avoid contamination and damage like scratches and cracks, our recommendations are:
Die must never be handled with bare hands
Avoid touching the active face
Do not store and transport die outside protective bags, tubes, boxes, sawn tape
Work only in ESD environments
Plastic tweezers or a soft vacuum tool are recommended to remove the silicon die from
the packing.
Rev1.0
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UBSC/ULSC IPDiA Capacitors - 100µm - NiAu finishing
Assembly by Soldering
Standard packing is tape & reel for die size larger than 0201 but silicon capacitors can be
provided within waffle pack, gelpak or sawing frame. Please contact the IPDIA sales contact for
drawing and references (sales@ipdia.com).
Pad opening
The top surface of the IPDiA silicon capacitors are protected with a mineral passivation. The
finishing of the contact pads are in nickel gold (generally 5µm nickel and 0.2µm gold) conforming
with the soldering process.
IPDiA recommends having an opening on the board which matches the pad of the capacitor
(size, position and spacing) – see figure 1. On the substrate, the metal layer can be larger than
the varnish coating opening size but in this case, the varnish coating opening has to be mirror
with the pad size of the capacitor. These recommendations will improve the die placement, tilting
and will avoid the contact between the solder paste and the bare silicon die (see figure 2).
Solder paste after reflow:
Varnish
coating
Figure 1: Solder paste after reflow - Targeted
Varnish coating
Figure 2: Solder paste after reflow - Rejected
Rev1.0
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