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Pin Connection Diagram
20-Pin Packages
FM3565
SCL
SDA
OVRD
I0
I1
I2
I3
I4
A/B
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
ASEL
WP
NC
MUXSEL
Y0
Y1
Y2
Y3
Y4
Pin Description
Pin Name
I [0:4]
Y [0:4]
SCL
OVRD
WP
NC
MUXSEL
A/B
ASEL
SDA
Description
Data Inputs w/Pullups (10K-40K)
Open-Drain Data Outputs
Serial Port Clock Input (120K pullup)
Override Input. Sets all outputs to 0
Write Protect Input
No Connect
Multiplex Select Input
Level Select Input
Address Select Input
Serial Port Data I/O (120K pullup)
2
FM3565 Rev. A.1
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FM3565 CPU CONFIGURATION CONTROLLER
Register/Multiplexer for Microprocessor VID
Functional Description
The FM3565 block diagram is shown in Figure 1.
Serial Output Port Register (SOPR)
(Address 000b and 001b)
MXSB MXSA
0
b7
0
b6
I5
b5
0
b4
Data Field
I3
b3
I2
b2
I1
B1
I0
b0
Operational Modes
During standard operation, the device will pass data to the Y-Port
either from the I-Port or from one of the internally stored Non-
Volatile Register values.
The I-port values are generated from the motherboard of the
system and may be hardwired or driven by another device. Pull-
up resistors are provided on the device to accommodate this
device being driven by open-drain output drivers. The device
expects standard CMOS input signals. The outputs (Y0-Y4)
operate in the open-drain mode. The OVRD (override) input, when
set to 0, will cause all the outputs to be set to 0. The WP signal, if
set to logic 1, will prevent data from being written to the non-volatile
register.
The functioning of this device is described by the truth table in
Table 1.
b7-b6 - Multiplexer Select Bits (MXSB,MXSA)
00 - Multiplexer passes the SOPR(A).
01 - Multiplexer passer the SOPR(B).
10 - Multiplexer defaults to passing the I-Port Value.
b5, b3-b0 - Data Field. New value to be output through the
multiplexer.
Parallel Input Port Register (PIPR)
(Address 002b)
Address Field
0
b7
0
b6
0
b5
I4
b4
Data Field
I3
b3
I2
b2
I1
B1
I0
b0
Output Port: Y0-Y4
The output port is an open-drain output to allow for easy connec-
tion to devices running at different voltage levels. The port is
always active and either passes the value on the I-Port or data
from one of the internal non-volatile registers (SOPRA/B). Chang-
ing the Mux Path is accomplished using the external hardware
controls – OVRD, MUXSEL, and A/B.
b7-b5 - Address field. Value is always 000
b4-b0 - Data Field. Value is equal to the value on the I-Port.
The external Port Register captures the value on the I-Port. Data
is latched into this register on the first clock after a start condition
is seen. This insures that a valid value will always be in this register
if it is read. This register is a-read only register with respect to the
IIC port.
Register Description
The FM3550/60 has 3 registers in total. These registers are made
up of a combination of read-only, write-only and read/write bits.
The two registers are listed below.
Serial Output Port Register A(SOPRA) Address: 00H
- A read/
write register that contains the new value of SOPRA.
Serial Output Port Register B(SOPRB) Address: 01H
- A read/
write register that contains the new value for SOPRB.
Parallel Input Port Register (PIPR) Address: 02H
- A read-only
register that is loaded with the 5-bit value of the I-Port.
3
FM3565 Rev. A.1
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FM3565 CPU CONFIGURATION CONTROLLER
Register/Multiplexer for Microprocessor VID
OVRD
0
0
1
1
1
MUXSEL
0
1
0
0
1
A/B
X
X
0
1
X
Mux_outputs
all 0's
Mux_inputs
From Non-volatile
register (SOPRB)
From Non-volatile
register (SOPRA)
Mux_inputs
Reading from the Registers
Data can be read from both of the internal registers. All reads are
non-destructive and do not change the value in the register or the
internal state of the device. When a start condition is received with
a read request, both registers can be read out in the following
sequence:
(1)
(2)
(3)
SOPRA: Serial Output Port Register A
SPORB: Serial Output Port Register B
PIPR: PORT-I Value
Table 1. Multiplexer Control Options
Multiplexer Logic
The output multiplexer logic determines what value is actually
output to the Y-port. The above table describes all the
combinations.
If so desired, only the SOPRA register can be read. This is
accomplished by issuing a stop command after the acknowledge
bit for the first byte is read. If no stop is issued, the device will output
the registers in the above sequence.
Writing to the Registers
Data is written to the SOPR registers through the serial port
interface. When a write request is received with the Start Address,
it is assumed that the intent is to write to the SOPR registers. The
value placed in the least 6 significant bits of the register contain the
new code to be placed in the SOPR A/B registers. The value of the
two most significant bits must contain the address of the destina-
tion register SOPRA or SOPRB.
The internal non-volatile latch takes about 10 ms to update its
data.
Serial Interface
The IIC Interface is a standard slave interface. As such, the device
will not generate its own clock. Data can be read from and written
into the device. Commands for reading and writing the registers
are generated by the Master.
START and STOP Conditions
SDA
Register Read Sequence
Slave
SOPRA
SOPRB
PIPR
S Address R A Register A Register A Register A P
SCL
START
Condition
STOP
Condition
S
1001110
1
A 00bbbbbb A 00bbbbbb A 00bbbbbb A P
Register Write Sequence
Slave
SOPRx
S Address W A Register A S
S
1001110
0
A xxbbbbbb
A S
This protocol uniquely defines START and STOP conditions. A
START condition is defined as a HIGH to LOW transition of the
SDA signal while SCL is HIGH. A STOP condition is defined as a
LOW to HIGH transition of the SDA signal while SCL is HIGH.
These are shown in Figure 2.
Device Addressing
The device uses 7-bit addressing. The address has been defined
as 1001 110 if the ASEL input is ‘1’ and 0110 111 if the ASEL input
is ‘0’. The address byte is the first byte of data sent after a start
condition. This is the only address that this device will respond to.
The device will not respond to the general call address 0000 000.
xx = Register Selection bits (MXSB and MXSA) xx = 00 selects
SOPRA, 01 selects SOPRB
Register Write Sequence using
Repeated Start Condition
Slave
SOPRA
Slave
SOPRx
S Address R A Register A S Address W A Register A P
S 1001110 1 A 00bbbbbb A S 1001110 0
A xxbbbbbb A P
Figure 4
4
FM3565 Rev. A.1
www.fairchildsemi.com
FM3565 CPU CONFIGURATION CONTROLLER
Register/Multiplexer for Microprocessor VID
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
)
Outputs 3-stated
Outputs Active (Note 2)
DC Input Diode Current (I
IK
) V
I
< 0V
DC Output Diode Current (I
OK
)
V
O
< 0V
V
O
> Vcc
DC Output Source/Sink Current (I
OH
/I
OL
)
DC V
CC
or Ground Current per
Supply Pin (I
CC
or Ground)
Storage Temperature Range (T
STG
)
-0.5V to +6.5V
-0.5V to +6.5V
-0.5V to +6.5V
-0.5 to V
CC
+0.5V
-50mA
-50mA
+50mA
±50mA
±100mA
-65
°
C to +150
°
C
Recommended Operating Conditions
(Note 3)
Power Supply
Input Voltage
Output Voltage (V
O
)
Output Current I
OL
Free Air Operating Temperature(TA)
Minimum Input Edge Rate (dt/dv)
V
IN
= 0.8V to 2.0V, V
CC
= 3.0V
3.0V to 5.5V
-0.3V to 5.5V
0V to V
CC
3mA
-0°C to +70°C
10ns/V
Note 1:
The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the “Electrical Characteristics” table are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will
define the conditions for actual device operation.
Note 2:
I
O
Absolute Maximum Rating must be observed.
Note 3:
Floating or unused pins (inputs or I/O’s) must be held HIGH or LOW.
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