EBD11UD8ADDA-7B datasheet, PDF

Datasheet> All Categories > storage> storage> EBD11UD8ADDA-7B

EBD11UD8ADDA-7B: Description1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks); Categorystorage storage; File Size208KB，19 Pages; ManufacturerELPIDA; Websitehttp://www.elpida.com/en

Download Datasheet Parametric Compare View All

EBD11UD8ADDA-7B Overview

1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)

EBD11UD8ADDA-7B Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	ELPIDA
Parts packaging code	MODULE
package instruction	DIMM, DIMM200,24
Contacts	200
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	DUAL BANK PAGE BURST
Maximum access time	0.75 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N200
JESD-609 code	e0
memory density	8589934592 bi
Memory IC Type	DDR DRAM MODULE
memory width	64
Number of functions	1
Number of ports	1
Number of terminals	200
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128MX64
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM200,24
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	235
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
self refresh	YES
Maximum standby current	0.048 A
Maximum slew rate	3.88 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	NO LEAD
Terminal pitch	0.6 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

Preview

Download Datasheet

View All

DATA SHEET

1GB DDR SDRAM SO-DIMM

EBD11UD8ADDA

(128M words

64 bits, 2 Ranks)

Description

The EBD11UD8ADDA is 128M words

64 bits, 2

ranks Double Data Rate (DDR) SDRAM Small Outline

Dual In-line Memory Module, mounting 16 pieces of

512M bits DDR SDRAM sealed in TCP package. Read

and write operations are performed at the cross points

of the CK and the /CK. This high-speed data transfer

is realized by the 2 bits prefetch-pipelined architecture.

Data strobe (DQS) both for read and write are available

for high speed and reliable data bus design. By setting

extended mode register, the on-chip Delay Locked

Loop (DLL) can be set enable or disable. This module

provides high density mounting without utilizing surface

mount technology. Decoupling capacitors are mounted

beside each TCP on the module board.

Note: Do not push the cover or drop the modules in

order to avoid mechanical defects, which may

result in electrical defects.

Features

•

200-pin socket type small outline dual in line memory

module (SO-DIMM)



PCB height: 31.75mm



Lead pitch: 0.6mm

•

2.5V power supply

•

Data rate: 333Mbps/266Mbps (max.)

•

2.5 V (SSTL_2 compatible) I/O

•

Double Data Rate architecture; two data transfers per

clock cycle

•

Bi-directional, data strobe (DQS) is transmitted

/received with data, to be used in capturing data at

the receiver

•

Data inputs, outputs and DM are synchronized with

DQS

•

4 internal banks for concurrent operation

(Components)

•

DQS is edge aligned with data for READs; center

aligned with data for WRITEs

•

Differential clock inputs (CK and /CK)

•

DLL aligns DQ and DQS transitions with CK

transitions

•

Commands entered on each positive CK edge; data

referenced to both edges of DQS

•

Data mask (DM) for write data

•

Auto precharge option for each burst access

•

Programmable burst length: 2, 4, 8

•

Programmable /CAS latency (CL): 2, 2.5

•

Refresh cycles: (8192 refresh cycles /64ms)



7.8µs maximum average periodic refresh interval

•

2 variations of refresh



Auto refresh



Self refresh

Document No. E0431E20 (Ver. 2.0)

Date Published April 2004 (K) Japan

URL: http://www.elpida.com

Elpida

Memory, Inc. 2003-2004

EBD11UD8ADDA-7B Related Products

	EBD11UD8ADDA-7B	EBD11UD8ADDA	EBD11UD8ADDA-6B	EBD11UD8ADDA-7A
Description	1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)	1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)	1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)	1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)
Is it Rohs certified?	incompatible	-	incompatible	incompatible
Maker	ELPIDA	-	ELPIDA	ELPIDA
Parts packaging code	MODULE	-	MODULE	MODULE
package instruction	DIMM, DIMM200,24	-	DIMM, DIMM200,24	DIMM, DIMM200,24
Contacts	200	-	200	200
Reach Compliance Code	unknow	-	unknow	unknow
ECCN code	EAR99	-	EAR99	EAR99
access mode	DUAL BANK PAGE BURST	-	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
Maximum access time	0.75 ns	-	0.7 ns	0.75 ns
Other features	AUTO/SELF REFRESH	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz	-	167 MHz	133 MHz
I/O type	COMMON	-	COMMON	COMMON
JESD-30 code	R-XDMA-N200	-	R-XDMA-N200	R-XDMA-N200
JESD-609 code	e0	-	e0	e0
memory density	8589934592 bi	-	8589934592 bi	8589934592 bi
Memory IC Type	DDR DRAM MODULE	-	DDR DRAM MODULE	DDR DRAM MODULE
memory width	64	-	64	64
Number of functions	1	-	1	1
Number of ports	1	-	1	1
Number of terminals	200	-	200	200
word count	134217728 words	-	134217728 words	134217728 words
character code	128000000	-	128000000	128000000
Operating mode	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	-	70 °C	70 °C
organize	128MX64	-	128MX64	128MX64
Output characteristics	3-STATE	-	3-STATE	3-STATE
Package body material	UNSPECIFIED	-	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	-	DIMM	DIMM
Encapsulate equivalent code	DIMM200,24	-	DIMM200,24	DIMM200,24
Package shape	RECTANGULAR	-	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	-	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	235	-	235	235
power supply	2.5 V	-	2.5 V	2.5 V
Certification status	Not Qualified	-	Not Qualified	Not Qualified
refresh cycle	8192	-	8192	8192
self refresh	YES	-	YES	YES
Maximum standby current	0.048 A	-	0.048 A	0.048 A
Maximum slew rate	3.88 mA	-	4.6 mA	3.88 mA
Maximum supply voltage (Vsup)	2.7 V	-	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.3 V	-	2.3 V	2.3 V
Nominal supply voltage (Vsup)	2.5 V	-	2.5 V	2.5 V
surface mount	NO	-	NO	NO
technology	CMOS	-	CMOS	CMOS
Temperature level	COMMERCIAL	-	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	NO LEAD	-	NO LEAD	NO LEAD
Terminal pitch	0.6 mm	-	0.6 mm	0.6 mm
Terminal location	DUAL	-	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED

Recommended Resources

Midea CFXB40-4, CFXB50-4 luxury timer automatic rice cooker circuit diagram

Simple timing circuit

Voltage stabilizing circuit with simultaneous adjustment of positive and negative voltages

Simple multi-waveform oscillator

Voltage stabilizing circuit using light-emitting diodes as zener diodes

Anti-theft alarm for cultural relics

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components