DATA SHEET
1GB DDR SDRAM SO-DIMM
EBD11UD8ADDA
(128M words
×
64 bits, 2 Ranks)
Description
The EBD11UD8ADDA is 128M words
×
64 bits, 2
ranks Double Data Rate (DDR) SDRAM Small Outline
Dual In-line Memory Module, mounting 16 pieces of
512M bits DDR SDRAM sealed in TCP package. Read
and write operations are performed at the cross points
of the CK and the /CK. This high-speed data transfer
is realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available
for high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. This module
provides high density mounting without utilizing surface
mount technology. Decoupling capacitors are mounted
beside each TCP on the module board.
Note: Do not push the cover or drop the modules in
order to avoid mechanical defects, which may
result in electrical defects.
Features
•
200-pin socket type small outline dual in line memory
module (SO-DIMM)
PCB height: 31.75mm
Lead pitch: 0.6mm
•
2.5V power supply
•
Data rate: 333Mbps/266Mbps (max.)
•
2.5 V (SSTL_2 compatible) I/O
•
Double Data Rate architecture; two data transfers per
clock cycle
•
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
•
Data inputs, outputs and DM are synchronized with
DQS
•
4 internal banks for concurrent operation
(Components)
•
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
referenced to both edges of DQS
•
Data mask (DM) for write data
•
Auto precharge option for each burst access
•
Programmable burst length: 2, 4, 8
•
Programmable /CAS latency (CL): 2, 2.5
•
Refresh cycles: (8192 refresh cycles /64ms)
7.8µs maximum average periodic refresh interval
•
2 variations of refresh
Auto refresh
Self refresh
Document No. E0431E20 (Ver. 2.0)
Date Published April 2004 (K) Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2003-2004
EBD11UD8ADDA
Serial PD Matrix
Byte No. Function described
0
1
2
3
4
5
6
7
8
9
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
Memory type
Number of row address
Number of column address
Number of DIMM ranks
Module data width
Module data width continuation
DDR SDRAM cycle time, CL = X
-6B
-7A,-7B
10
SDRAM access from clock (tAC)
-6B
-7A, -7B
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
SDRAM device attributes:
Minimum clock delay back-to-back
column access
SDRAM device attributes:
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes: /CS latency
SDRAM device attributes: /WE latency
SDRAM module attributes
SDRAM device attributes: General
Minimum clock cycle time at
CL = X –0.5
-6B, -7A
-7B
24
Maximum data access time (tAC) from
clock at CL = X –0.5
-6B
-7A, -7B
25 to 26
27
Minimum row precharge time (tRP)
-6B
-7A, -7B
Bit7
1
0
0
0
0
0
0
0
Bit6
0
0
0
0
0
0
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
1
1
Bit5 Bit4
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
1
Bit3
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
Bit2
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
Bit1 Bit0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
Hex value
80H
08H
07H
0DH
0BH
02H
40H
00H
04H
60H
75H
70H
75H
00H
82H
08H
00H
01H
0EH
04H
0CH
01H
02H
20H
C0H
75H
A0H
70H
75H
00H
48H
50H
18ns
20ns
0.70ns*
1
0.75ns*
1
0.70ns*
1
0.75ns*
1
None
7.6µs
Self refresh
×
8
Not used
1 CLK
2,4,8
4
2, 2.5
0
1
Unbuffered
VDD ± 0.2V
CL = 2*
1
Comments
128 bytes
256 bytes
DDR SDRAM
13
11
2
64 bits
0
SSTL2.5V
CL = 2.5*
1
Voltage interface level of this assembly 0
0
0
0
0
0
1
0
0
0
0
0
SDRAM device attributes: /CAS latency 0
0
0
0
1
0
1
0
0
0
0
0
Data Sheet E0431E20 (Ver. 2.0)
5