MFRC631
High-performance ISO/IEC 14443 A/B frontend
Rev. 4.2 — 27 April 2016
227442
Product data sheet
COMPANY PUBLIC
1. General description
MFRC631, the cost efficient NFC frontend for payment.
The MFRC631 multi-protocol NFC frontend IC supports the following operating modes:
•
Read/write mode supporting ISO/IEC 14443A/MIFARE
•
Read/write mode supporting ISO/IEC 14443B
The MFRC631’s internal transmitter is able to drive a reader/writer antenna designed to
communicate with ISO/IEC 14443A/MIFARE cards and transponders without additional
active circuitry. The digital module manages the complete ISO/IEC 14443A framing and
error detection functionality (parity and CRC).
The MFRC631 supports MIFARE Classic 1K, MIFARE Classic 4K, MIFARE Ultralight,
MIFARE Ultralight C, MIFARE Plus and MIFARE DESFire products. The MFRC631
supports MIFARE higher transfer speeds of up to 848 kbit/s in both directions.
The MFRC631 supports layer 2 and 3 of the ISO/IEC 14443B reader/writer
communication scheme except anticollision. The anticollision needs to be implemented in
the firmware of the host controller as well as in the upper layers.
The following host interfaces are supported:
•
Serial Peripheral Interface (SPI)
•
Serial UART (similar to RS232 with voltage levels dependent on pin voltage supply)
•
I
2
C-bus interface (two versions are implemented: I2C and I2CL)
The MFRC631 supports the connection of a secure access module (SAM). A dedicated
separate I
2
C interface is implemented for a connection of the SAM. The SAM can be used
for high secure key storage and acts as a very performant crypto coprocessor. A
dedicated SAM is available for connection to the MFRC631.
2. Features and benefits
Includes NXP ISO/IEC14443-A, Innovatron ISO/IEC14443-B and NXP MIFARE
Crypto 1 intellectual property
licensing rights
High-performance multi-protocol NFC frontend for transfer speed up to 848 kbit/s
Supports ISO/IEC 14443 A/MIFARE, ISO/IEC 14443 B
Supports MIFARE Classic encryption by hardware in read/write mode
Allows to read MIFARE Ultralight, MIFARE Classic 1K, MIFARE Classic 4K, MIFARE
DESFire EV1, MIFARE DESFire EV2 and MIFARE Plus cards
NXP Semiconductors
MFRC631
High-performance ISO/IEC 14443 A/B frontend
Low-power card detection
Compliance to “EMV contactless protocol specification V2.3.1” on RF level can be
achieved
Antenna connection with minimum number of external components
Supported host interfaces:
SPI up to 10 Mbit/s
I
2
C-bus interfaces up to 400 kBd in Fast mode, up to 1000 kBd in Fast mode plus
RS232 Serial UART up to 1228.8 kBd, with voltage levels dependent on pin
voltage supply
Separate I
2
C-bus interface for connection of a secure access module (SAM)
FIFO buffer with size of 512 byte for highest transaction performance
Flexible and efficient power saving modes including hard power down, standby and
low-power card detection
Cost saving by integrated PLL to derive system clock from 27.12 MHz RF quartz
crystal
3 V to 5.5 V power supply
Up to 8 free programmable input/output pins
Typical operating distance in read/write mode for communication to a
ISO/IEC 14443A/MIFARE Card up to 12 cm, depending on the antenna size and
tuning
3. Quick reference data
Table 1.
Symbol
V
DD
V
DD(PVDD)
V
DD(TVDD)
I
pd
I
DD
I
DD(TVDD)
T
amb
T
stg
[1]
[2]
Quick reference data
Parameter
supply voltage
PVDD supply voltage
TVDD supply voltage
power-down current
supply current
TVDD supply current
ambient temperature
storage temperature
no supply voltage applied
PDOWN pin pulled HIGH
[2]
[1]
Conditions
Min
3
3
3
-
-
-
25
40
Typ
5
5
5
8
17
100
+25
+25
Max
5.5
V
DD
5.5
40
20
250
+85
+100
Unit
V
V
V
nA
mA
mA
C
C
VDD(PVDD) must always be the same or lower voltage than VDD.
I
pd
is the sum of all supply currents
MFRC631
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.2 — 27 April 2016
227442
2 of 119
NXP Semiconductors
MFRC631
High-performance ISO/IEC 14443 A/B frontend
4. Ordering information
Table 2.
Ordering information
Package
Name
MFRC63102HN/TRAYB
[1]
MFRC63102HN/TRAYBM
[2]
MFRC63102HN/T/R
[3]
[1]
[2]
[3]
Delivered in one tray
Delivered in five trays
Delivered on reel with 6000 pieces
Type number
Description
Version
HVQFN32
plastic thermal enhanced very thin quad flat package; no SOT617-1
leads; MSL1, 32 terminals + 1 central ground; body 5
5
0.85 mm
5. Block diagram
The analog interface handles the modulation and demodulation of the antenna signals for
the contactless interface.
The contactless UART manages the protocol dependency of the contactless interface
settings managed by the host.
The FIFO buffer ensures fast and convenient data transfer between host and the
contactless UART.
The register bank contains the settings for the analog and digital functionality.
REGISTER BANK
ANTENNA
ANALOG
INTERFACE
CONTACTLESS
UART
FIFO
BUFFER
SERIAL UART
SPI
I
2
C-BUS
HOST
001aaj627
Fig 1.
Simplified block diagram of the MFRC631
MFRC631
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.2 — 27 April 2016
227442
3 of 119
NXP Semiconductors
MFRC631
High-performance ISO/IEC 14443 A/B frontend
6. Pinning information
27 IFSEL1
26 IFSEL0
25 PVDD
24 SDA
(1)
32 IRQ
31 IF3
30 IF2
29 IF1
terminal 1
index area
TDO
TDI
TMS
TCK
SIGIN
SIGOUT
DVDD
VDD
1
2
3
4
5
6
7
8
28 IF0
23 SCL
22 CLKOUT
21 PDOWN
20 XTAL2
19 XTAL1
18 TVDD
17 TX1
heatsink
AUX1 10
RXP 12
RXN 13
VMID 14
TX2 15
AVDD
TVSS 16
AUX2 11
9
001aam004
Transparent top view
(1) Pin 33 VSS - heatsink connection
Fig 2.
Pinning configuration HVQFN32 (SOT617-1)
6.1 Pin description
Table 3.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Pin description
Type
O
I
I
I
I
O
PWR
PWR
PWR
O
O
I
I
PWR
O
PWR
O
PWR
I
Description
test data output for boundary scan interface
test data input boundary scan interface
test mode select boundary scan interface
test clock boundary scan interface
Contactless communication interface output.
Contactless communication interface input.
digital power supply buffer
[1]
power supply
analog power supply buffer
[1]
auxiliary outputs: Pin is used for analog test signal
auxiliary outputs: Pin is used for analog test signal
receiver input pin for the received RF signal.
receiver input pin for the received RF signal.
internal receiver reference voltage
[1]
transmitter 2: delivers the modulated 13.56 MHz carrier
transmitter ground, supplies the output stage of TX1, TX2
transmitter 1: delivers the modulated 13.56 MHz carrier
transmitter voltage supply
crystal oscillator input: Input to the inverting amplifier of the oscillator. This is pin is also the
input for an externally generated clock (fosc = 27,12 MHz)
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Symbol
TDO
TDI
TMS
TCK
SIGIN
SIGOUT
DVDD
VDD
AVDD
AUX1
AUX2
RXP
RXN
VMID
TX2
TVSS
TX1
TVDD
XTAL1
MFRC631
Product data sheet
COMPANY PUBLIC
Rev. 4.2 — 27 April 2016
227442
4 of 119
NXP Semiconductors
MFRC631
High-performance ISO/IEC 14443 A/B frontend
Table 3.
Pin
20
21
22
23
24
25
26
27
28
29
30
31
32
33
[1]
Pin description
…continued
Type
O
I
O
O
I/O
PWR
I
I
I/O
I/O
I/O
I/O
O
PWR
Description
crystal oscillator output: output of the inverting amplifier of the oscillator
Power Down
clock output
Serial Clock line
Serial Data Line
pad power supply
host interface selection 0
host interface selection 1
interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, I
2
C, I
2
C-L
interface pin, multifunction pin: Can be assigned to host interface SPI, I
2
C, I
2
C-L
interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, I
2
C, I
2
C-L
interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, I
2
C, I
2
C-L
interrupt request: output to signal an interrupt event
ground and heatsink connection
Symbol
XTAL2
PDOWN
CLKOUT
SCL
SDA
PVDD
IFSEL0
IFSEL1
IF0
IF1
IF2
IF3
IRQ
VSS
This pin is used for connection of a buffer capacitor. Connection of a supply voltage might damage the device.
MFRC631
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.2 — 27 April 2016
227442
5 of 119
京公网安备 11010802033920号
EEWORLD
