SL74HC08
Quad 2-Input AND Gate
High-Performance Silicon-Gate CMOS
The SL74HC08 is identical in pinout to the LS/ALS08. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC08N Plastic
SL74HC08D SOIC
T
A
= -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
A
L
L
H
PIN 14 =V
CC
PIN 7 = GND
H
B
L
H
L
H
Output
Y
L
L
L
H
SLS
System Logic
Semiconductor
SL74HC08
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±25
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
Min
2.0
0
-55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤V
CC
.
Unised inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
SLS
System Logic
Semiconductor
SL74HC08
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
PLH
, t
PHL
Parameter
Maximum Propagation Delay, Input A or B to
Output Y (Figures 1 and 2)
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
Maximum Input Capacitance
V
2.0
4.5
6.0
2.0
4.5
6.0
-
Guaranteed Limit
25
°C
to
-55°C
75
15
13
75
15
13
10
≤85°C
95
19
16
95
19
16
10
≤125°C
110
22
19
110
22
19
10
Unit
ns
t
TLH
, t
THL
ns
C
IN
pF
Power Dissipation Capacitance (Per Gate)
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
Typical @25°C,V
CC
=5.0 V
20
pF
Figure 1 Switching Waveforms.
Figure 2. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
SLS
System Logic
Semiconductor
Renesas Electronics MCUs
京公网安备 11010802033920号
EEWORLD
