HANBit
HSD128M72B9K
Synchronous DRAM Module 1024Mbyte (128Mx72Bit), 8K Ref., 3.3V
ECC Unbuffered SO-DIMM,
Part No. HSD128M72B9K
GENERAL DESCRIPTION
The HSD128M72B9K is a 128M x 72 bit Synchronous Dynamic RAM high density memory module. The module
consists of nine CMOS 128M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 144-pin glass-
epoxy substrate. One or two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each
SDRAM. The HSD128M72B9K is a SO-DIMM(Small Outline Dual in line Memory Module) and is intended for mounting
into 144-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O
transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high performance memory system applications All module components
may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
•
JEDEC standard 3.3V power supply
•
Burst mode operation
•
Auto & self refresh capability (8192 Cycles/64ms)
•
LVTTL compatible with multiplexed address
•
Separate power and ground planes to improve immunity
•
Height : 1.250 inches
•
MRS cycle with address key programs
- CAS latency (2 & 3)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
•
All inputs are sampled at the positive going edge of the system clock
•
The used device is 16M x 8bit x 4Banks Synchronous DRAM
•
Part Identification
HSD128M72B9K-F/10L : 100MHz (CL=3)
HSD128M72B9K-F/10 : 100MHz (CL=2)
HSD128M72B9K-F/12 : 125MHz (CL=3)
HSD128M72B9K-F/13 : 133MHz (CL=3)
** F means Auto & Self refresh with Low-Power (3.3V)
URL :
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REV.0.0(January. 2003)
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HANBit Electronics Co.,Ltd.
HANBit
PIN ASSIGNMENT
No.
1
3
5
7
9
11
13
15
`17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
Front
Vss
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
Vss
DQM0
DQM1
VCC
A0
A1
A2
Vss
DQ8
DQ9
DQ10
DQ11
VCC
DQ12
DQ13
DQ14
DQ15
Vss
CB0
CB1
No.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
Back
Vss
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
Vss
DQM4
DQM5
VCC
A3
A4
A5
Vss
DQ40
DQ41
DQ42
DQ43
VCC
DQ44
DQ45
DQ46
DQ47
Vss
CB4
CB5
No.
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
CKE0
VCC
/CAS
CKE1
A12
135
137
139
141
143
Front
/CS1
NC
Vss
CB2
CB3
VCC
DQ16
DQ17
DQ18
DQ19
Vss
DQ20
DQ21
DQ22
DQ23
VCC
A6
A8
Vss
A9
A10_AP
VCC
DQM2
DQM3
Vss
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
Vss
**SDA
VCC
No.
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
HSD128M72B9K
Back
NC
CLK1
Vss
CB6
CB7
VCC
DQ48
DQ49
DQ50
DQ51
Vss
DQ52
DQ53
DQ54
DQ55
VCC
A7
BA0
Vss
BA1
A11
VCC
DQM6
DQM7
Vss
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
Vss
**SCL
VCC
Voltage Key
61
63
65
67
69
CLK0
VCC
/RAS
/WE
/CS0
62
64
66
68
70
** These pins should be NC in the system which does not support SPD
URL :
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REV.0.0(January. 2003)
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Functional Block Diagram
/CS1
/CS0
/CS
/CS
HSD128M72B9K
DQM0
DQ(0:7)
Add(0:12)
BA(0:1)
/RAS
/CAS
/WE
CKE(0:1)
CLK0
DQM
DQ(0:7)
BA(0:1)
/RAS
/CAS
/WE
CKE(0:1)
CLK
/CS
DQM4
DQ(32:39)
DQM
DQ(0:7)
/CS
Add(0:12)
Add(0:12)
BA(0:1)
U1L
U1U
/RAS
/CAS
/WE
CKE(0:1)
CLK1
CLK
U5L
U5U
DQM1
DQ(8:15)
DQM
/CS
/CS
DQ(0:7)
Add(0:12)
BA(0:1)
/RAS
/CAS
/WE
CKE(0:1)
CLK
DQM5
DQ(40:47)
DQM
DQ(0:7)
/CS
/CS
Add(0:12)
BA(0:1)
U2L
U2U
/RAS
/CAS
/WE
CKE(0:1)
CLK
U6L
U6U
DQM2
DQ(16:23)
DQM
DQ(0:7)
/CS
/CS
DQM6
DQ(48:55)
DQM
DQ(0:7)
/CS
/CS
Add(0:12)
BA(0:1)
/RAS
/CAS
/WE
CKE(0:1)
CLK
Add(0:12)
BA(0:1)
U3L
U3U
/RAS
/CAS
/WE
CKE(0:1)
CLK
U7L
U7U
DQM3
DQ(24:31)
DQM
DQ(0:7)
/CS
/CS
DQM7
DQ(56:63)
DQM
/CS
/CS
Add(0:12)
BA(0:1)
/RAS
/CAS
/WE
CKE(0:1)
CLK
DQ(0:7)
Add(0:12)
BA(0:1)
/RAS
/CAS
/WE
CKE(0:1)
CLK
U4L
U4U
U8L
U8U
DQM1
CB(0:7)
DQM
DQ(0:7)
/CS
/CS
Add(0:12)
BA(0:1)
/RAS
/CAS
/WE
CKE(0:1)
CLK
Serial PD
U9L
U9U
SCL
A0
A1
A2
SDA
WP
47K
SA0
SA1
SA2
VCC
One or two 0.1uF
Capacitors
per each SDRAM
To all SDRAMs
VSS
URL :
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REV.0.0(January. 2003)
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PIN FUNCTION DESCRIPTION
Pin
CLK0~CLK1
/CS0~/CS1
Name
System clock
Chip select
Input Function
HSD128M72B9K
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9, CA11
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with /RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with /CAS
low. Enables column access.
Enables write operation and row precharge.
Latches data in starting from /CAS, /WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
Data inputs/outputs are multiplexed on the same pins.
Check bits for ECC
Power and ground for the input buffers and the core logic.
CKE0, CKE1
Clock enable
A0 ~ A12
BA0 ~ BA1
/RAS
/CAS
/WE
DQM0 ~ 7
DQ0 ~ 63
CB0~7
V
CC
/ V
SS
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input / output mask
Data input / output
Check bit
Power supply / ground
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
Storage Temperature
Short Circuit Output Current
Notes:
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded.
restricted to the conditions as detailed in the operational sections of this data sheet.
rating conditions for extended periods may affect device reliability.
Functional operation should be
Exposure to absolute maximum
SYMBOL
V
IN
, V
OUT
Vcc
P
D
T
STG
I
OS
RATING
-1V to 4.6V
-1V to 4.6V
18W
-55oC to 150oC
50mA
URL :
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REV.0.0(January. 2003)
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HANBit Electronics Co.,Ltd.
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DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70° C) )
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input leakage current
Notes :
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
£
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
£
3ns.
3. Any input 0V
£
V
IN
£
V
DDQ
.
SYMBOL
Vcc
V
IH
V
IL
V
OH
V
OL
I
LI
MIN
3.0
2.0
-0.3
2.4
-
-10
TYP.
3.3
3.0
0
-
-
-
MAX
3.6
Vcc+0.3
0.8
-
0.4
10
HSD128M72B9K
UNIT
V
V
V
V
V
uA
NOTE
1
2
I
OH
= -2mA
I
OL
= 2mA
3
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(V
CC
= 3.3V, T
A
= 23° C, f = 1MHz, VREF =1.4V
±
200 mV)
PARAMETER
Input Capacitance (A0~A12, BA0~BA1)
Input Capacitance (/RAS, /CAS, /WE)
Input Capacitance (CKE0 ~ CKE1)
Input Capacitance (CLK0 ~ CLK1)
Input Capacitance (/CS0 ~ /CS1)
Input Capacitance (DQM0 ~ DQM1)
Data Input Capacitance (DQ0 ~ DQ63)
Data Input Capacitance (CB0 ~ CB7)
SYMBOL
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
IN6
C
IN7
C
OUT
MIN
45
45
35
25
35
10
15
15
MAX
90
90
60
45
60
25
30
30
UNITS
pF
pF
pF
pF
pF
pF
pF
pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70° C)
PARAMETER
Operating current
(One bank active)
SYMBOL
TEST CONDITION
Burst length = 1
I
CC1
t
RC
³
t
RC
(min)
I
O
= 0mA
I
CC2
P
I
CC2
PS
CKE
£
V
IL
(max)
t
CC
=10ns
CKE & CLK
£
V
IL
(max)
t
CC
=¥
CKE
³
V
IH
(min)
Precharge standby current in
non power-down mode
I
CC2
N
CS*
³
V
IH
(min),
time during 20ns
t
CC
=10ns
Input signals are changed one
360
mA
36
36
mA
mA
1080
990
990
990
mA
1
VERSION
-13
-12
-10
-10L
UNIT
NOTE
Precharge standby current in
power-down mode
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REV.0.0(January. 2003)
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