V-Data
Synchronous DRAM
General Description
The VDS6632A4A are four-bank Synchronous
DRAMs organized as 524,288 words x 32 bits x 4
banks,
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
VDS6632A4A
512K x 32 Bit x 4 Banks
Features
•JEDEC
standard LVTTL 3.3V power supply
•MRS
Cycle with address key programs
-CAS Latency (2 & 3)
-Burst Length (1,2,3,8,& full page)
-Burst Type (sequential & Interleave)
•4
banks operation
•All
inputs are sampled at the positive edge of
the system clock
•Burst
Read single write operation
•Auto
& Self refresh
•4096
refresh cycle
•DQM
for masking
•Package:86-pins
400 mil TSOP-Type II
Ordering Information.
Part No.
VDS6632A4A-5
VDS6632A4A-5.5
VDS6632A4A-6
Frequency
200Mhz
183Mhz
166Mhz
Interface
LVTTL
LVTTL
LVTTL
Package
400mil 86pin TSOPII
400mil 86pin TSOPII
400mil 86pin TSOPII
Pin Assignment
V
DD
D Q0
V
DD Q
D Q1
D Q2
V
SSQ
D Q3
D Q4
V
DD Q
DQ 5
DQ 6
V
SSQ
DQ 7
NC
V
DD
DQM 0
WE
CA S
RA S
CS
NC
BA0
BA1
A1 0/A P
A0
A1
A2
D QM 2
V
DD
NC
DQ 16
V
S SQ
DQ 17
DQ 18
V
DD Q
DQ 19
DQ 20
V
S SQ
DQ 21
DQ 22
V
DD Q
D Q 23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
S S
DQ15
V
S SQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
S SQ
DQ10
DQ9
V
DD Q
DQ8
NC
V
S S
DQM 1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM 3
V
S S
NC
DQ31
V
DD Q
DQ30
DQ29
V
SSQ
DQ28
DQ27
V
DD Q
DQ26
DQ25
V
SSQ
DQ24
V
S S
86-pin plastic TSOP II 400mil
Rev 1.0 April, 2001
1
V-Data
Pin Description
PIN
CLK
CKE
NAME
System Clock
Clock Enable
FUNCTION
Active on the positive edge to sample all inputs.
VDS6632A4A
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS
Chip Select
Disables or Enables device operation by masking or enabling all input
except CLK, CKE and DQM0 ~ DQM3
A0~A11
Address
Row / Column address are multiplexed on the same pins.
Row address : RA0~RA10
Column address : CA0~CA7
BA0~BA1 Banks Select
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
DQ0~DQ31 Data
DQM0~3
/RAS
/CAS
/WE
Data Mask
Row Address Strobe
Column Address Strobe
Write Enable
Data inputs / outputs are multiplexed on the same pins.
Makes data output Hi-Z,
Latches row addresses on the positive edge of the CLK with /RAS low
Latches Column addresses on the positive edge of the CLK with /CAS low
Enables write operation and row recharge.
Power and Ground for the input buffers and the core logic.
Power supply for output buffers.
This pin is recommended to be left No Connection on the device.
VDD/VSS Power Supply/Ground
V
DDQ
/V
SSQ
Data Output Power/Ground
NC
No Connection
Block Diagram
CLK
CKE
Address
Clock
Generator
Bank3
Bank2
Bank1
Row Decoder
Mode
Register
Address
Buffer
&
Refresh
Counter
Bank0
Amplifier
DQM
Command Decoder
/RAS
/CAS
/WE
Control Logic
/CS
Data Latch
Column
Address
Buffer
&
Refresh
Counter
Column Decoder
Data Control Circuit
DQ
Rev 1.0 April, 2001
2
V-Data
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
out
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
VDS6632A4A
Unit
V
V
℃
W
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Condition
Voltage referenced to Vss = 0V, T
A
= 0 to 70
℃
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
Min
3.0
2.0
-0.3
2.4
-
-5
-5
Typ
3.3
3.0
0
-
-
-
-
Max
3.6
V
DD
+0.3
0.8
-
0.4
5
5
Unit
V
V
V
V
V
uA
uA
1
2
I
OH
=-2mA
I
OL
=2mA
3
4
Note
Note :
1. V
IH
(max)=4.6V AC for pulse width
≦
10ns acceptable.
2.V
IL
(min)=-1.5V AC for pulse width
≦
10ns acceptable.
3.Any input 0V
≦
V
IN
≦
V
DD
+ 0.3V, all other pins are not under test = 0V.
4.Dout is disabled, 0V
≦
V
OUT
≦
V
DD
.
AC Operating Condition
Voltage referenced to Vss = 0V, T
A
= 0 to 70
℃
Parameter
AC input high / low level voltage
Input timing measurement reference level voltage
Input rise / fall time
Output timing measurement reference level
Output load capacitance for access time measurement
Note:
1. 3.15V
≦
V
DD
≦
3.6V is applied for VDS6632A4A5.
Symbol
V
IH
/ V
IL
Vtrip
TR / tF
Voutfef
CL
Value
2.4 / 0.4
1.4
1
1.4
30
Unit
V
V
Ns
V
pF
2
Note
2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details,
refer to AC/DC output load circuit.
Rev 1.0 April, 2001
3
V-Data
Capacitance
TA=25℃, f-=1Mhz, VDD=3.3V
Parameter
Input capacitance
CLK
A0~A11,BA0,BA1,CKE,/CS,/RAS,
/CAS,/WE,DQM
Data input / output capacitance DQM
CI/O
4
Pin
Symbol
Cl1
Cl2
VDS6632A4A
Min
2.5
2.5
Max
4
5
Unit
pF
pF
6.5
pF
Output load circuit
3.3 V
1200 ohms
V
OH
(DC) = 2.4V,I
OH
= -2mA
V
OL
(DC) = 0.4V,I
OL
= 2mA
50 pF
870 ohms
Output
DC Characteristics I
Parameter
Input leakage current
Output leakage current
Output high voltage
Output low voltage
I
LI
I
LO
V
OH
V
OL
Symbol
Min
-1
-1.5
2.4
-
Max
1
1.5
-
0.4
Unit
uA
uA
V
V
Note
1
2
I
OH
= -2mA
I
OL
= 2mA
Note :
1.V
IN
= 0 TO 3.6V, All other pins are not tested under V
IN
= 0V.
2.D
OUT
is disabled, V
OUT
= 0 to 3.6.
Rev 1.0 April, 2001
4
V-Data
DC Characteristics II
Speed
Parameter
Symbol
Test condition
-5
Burst length=1, One bank active
Operating Current
Precharge standby
current in power down
mode
IDD2PS
CKE≦V
IL
(max), tCK=∞
CKE≧V
IH
(min), /CS≧V
IH
(min),
tCK=min input signals are
Precharge standby
current in Non power
down mode
IDD2NS
Input signals are stable.
Active standby current IDD3P
in power down mode
IDD3PS
CKE≦V
IL
(max), tCK=min
CKE≦V
IL
(max), tCK=∞
CKE≧V
IH
(min), /CS≧V
IH
(min),
tCK=min input signals are
Active standby current IDD3N
in Non power down
mode
IDD3NS
Input signals are stable.
Burst mode operating
IDD4
current
Auto refresh current
Self refresh current
IDD5
active
IDD6
CKE≦0.2V
1
All banks active
tRRC≧tRRC(min), All banks
250
240
t
CK
≧t
CK
(min),I
OL
=0 mA
280
270
changed one time during 2clks. All
other pins
≧VDD-0.2V
or
≦
0.2V
CKE≧V
IH
(min), tCK=∞
20
30
6
IDD2N
changed one time during 2clks. All
other pins
≧VDD-0.2V
or
≦
0.2V
CKE≧V
IH
(min), tCK=∞
12
15
2
IDD1
tRC≧tRC(min),I
OL
=0mA
CKE≦V
IL
(max), tCK=min
210
200
-5.5
VDS6632A4A
Unit
-6
190
mA
Note
1
IDD2P
2
mA
mA
mA
5
mA
260
mA
1
230
mA
mA
2
Note:
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output
open.
2. Min. of tRRC is shown at AC characteristics.
Rev 1.0 April, 2001
5
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