Sets the drive strength of the output drivers to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID)
or HSTL (LOW) compatible. Used in conjunction with V
DDQ
to set the interface levels.
Power supply for the device core and inputs
Power supply for the device outputs. When utilizing 2.5V LVTTL outputs, V
DDQ
should be
connected to V
DD
.
Power supply return for all power
A / V
REF
I
Adjustable
1
G
GL
Qn
RxS
TxS
V
DD
V
DDQ
GND
I
I
O
I
I
LVTTL
5
LVTTL
5
Adjustable
2
3 Level
3
3 Level
3
PWR
PWR
PWR
NOTES: 1. Inputs are capable of translating the following interface standards. User can select between:
Single-ended 2.5V LVTTL levels
Single-ended 1.8V LVTTL levels
or
Differential 2.5V/1.8V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL levels
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate V
DDQ
voltage.
3. 3 level inputs are static inputs and must be tied to V
DD
or GND or left floating. These inputs are not hot-insertable or over-voltage tolerant.
4. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize
the possibility of runt pulses or be able to tolerate them in down stream circuitry.
5. Pins listed as LVTTL inputs will accept 2.5V signals when RxS = HIGH or 1.8V signals when RxS = LOW or MID.
Absolute Maximum Ratings
1
Symbol
V
DD
V
DDQ
V
I
V
O
V
REF
T
STG
T
J
Power Supply Voltage
Output Power Supply
2
Input Voltage
Output Voltage
3
Reference Voltage
3
Storage Temperature
Junction Temperature
2
Description
Max
-0.5 to +3.6
-0.5 to +3.6
-0.5 to +3.6
-0.5 to V
DDQ
+0.5
-0.5 to +3.6
-65 to +165
150
Unit
V
V
V
V
V
°C
°C
Note:
1.These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device
reliability.
2. V
DDQ
and V
DD
internally operate independently. No power sequencing requirements need to be met.
3. Not to exceed 3.6V.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
3 of 19
November 2006
rev 0.2
Capacitance
1,2
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
ASM2P5T905A
Parameter
Input Capacitance
Min
Typ
3.5
Max
Unit
pF
Notes:
1. This parameter is measured at characterization but not tested.
2. Capacitance applies to all inputs except RxS and TxS.
Recommended Operating Range
Symbol
T
A
V
DD1
V
DDQ1
Description
Ambient Operating Temperature
Internal Power Supply Voltage
HSTL Output Power Supply Voltage
Extended HSTL and 1.8V LVTTL Output Power
Supply Voltage
2.5V LVTTL Output Power Supply Voltage
Termination Voltage
Min
-40
2.4
1.4
1.65
Typ
+25
2.5
1.5
1.8
V
DD
V
DDQ
/ 2
Max
+85
2.6
1.6
1.95
Unit
°C
V
V
V
V
V
V
T
NOTE:
1. All power supplies should operate in tandem. If V
DD
or V
DDQ
is at maximum, then V
DDQ
or V
DD
(respectively) should be at maximum, and vice-versa.
Input/Output Selection
1
Input
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
Output
Input
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
Output
2.5V LVTTL
eHSTL
1.8V LVTTL
HSTL
NOTE:
1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations of input and output interfaces. Single-Ended (SE) inputs in a single-ended
mode require the A/V
REF
pin to be connected to GND. Differential Single-Ended (DSE) is for single-ended operation in differential mode, requiring a V
REF
.
Differential (DIF) inputs are used only in differential mode.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
4 of 19
November 2006
rev 0.2
DC Electrical Characteristics over Operating Range
Symbol
V
IHH
V
IMM
V
ILL
I
3
ASM2P5T905A
Parameter
Input HIGH Voltage Level
Input MID Voltage Level
1
Input LOW Voltage Level
1
3-Level Input DC Current
(RxS, TxS)
1
Test Conditions
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
V
IN
= V
DD
HIGH Level
V
IN
= V
DD
/2
MID Level
V
IN
= GND
LOW Level
Min
V
DD-
0.4
V
DD
/2- 0.2
Max
V
DD
/2 + 0.2
0.4
200
+50
Unit
V
V
V
µA
-50
-200
NOTE:
1. These inputs are normally wired to V
DD
, GND, or left floating. Internal termination resistors bias unconnected inputs to V
DD
/2.
DC Electrical Characteristics over Operating Range for HSTL
1
Symbol
Parameter
Input Characteristics
I
IH
I
IL
V
IK
V
IN
V
DIF
V
CM
V
IH
V
IL
V
REF
Input HIGH Current
9
Input LOW Current
Clamp Diode Voltage
DC Input Voltage
DC Differential Voltage
2,8
DC Common Mode Input
Voltage
3,8
4,5,8
DC Input HIGH
DC Input LOW
4,6,8
Single-Ended Reference
Voltage
4,8
Output HIGH Voltage
Output LOW Voltage
9
Test Conditions
V
DD
= 2.6V
V
I
= V
DDQ
/GND
Min
Typ
7
Max
±5
Unit
µA
V
V
V
mV
mV
mV
mV
V
V
DD
= 2.6V
V
I
= GND/V
DDQ
V
DD
= 2.4V, I
IN
= -18mA
-0.3
0.2
680
V
REF
+ 100
-0.7
±5
- 1.2
+3.6
900
V
REF
-100
750
750
I
OH
= -8mA
I
OH
= -100µA
I
OL
= 8mA
I
OL
= 100µA
V
DDQ
- 0.4
V
DDQ
- 0.1
0.4
0.1
Output Characteristics
V
OH
V
OL
V
V
V
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. V
DIF
specifies the minimum input differential voltage (V
TR
- V
CP
) required for switching where V
TR
is the "true" input level and V
CP
is the "complement" input
level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential
voltage must be achieved to guarantee switching to a new state.
3. V
CM
specifies the maximum allowable range of (V
TR
+ V
CP
) /2. Differential mode only.
4. For single-ended operation, in differential mode, A/V
REF
is tied to the DC voltage V
REF
.
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at V
DD
= 2.5V, V
DDQ
= 1.5V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface
table should be referenced.
9. For differential mode (RxS = LOW), A and A/V
REF
must be at the opposite rail
.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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