AS29LV800T-80TC datasheet, PDF

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AS29LV800T-80TC: Description3V 1M】8/512k】16 cmos flash eeprom; File Size195KB，24 Pages; ManufacturerANADIGICS; Websitehttp://www.anadigics.com

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AS29LV800T-80TC Overview

3V 1M】8/512k】16 cmos flash eeprom

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October 2000

AS29LV800

3V 1M×8/512K×16 CMOS Flash EEPROM

Features

• Organization: 1M×8/512K×16

• Sector architecture

- One 16K; two 8K; one 32K; and fifteen 64K byte sectors

- One 8K; two 4K; one 16K; and fifteen 32K word sectors

- Boot code sector architecture—T (top) or B (bottom)

- Erase any combination of sectors or full chip

• Single 2.7-3.6V power supply for read/write operations

• Sector protection

• High speed 80/90/120 ns address access time

• Automated on-chip programming algorithm

- Automatically programs/verifies data at specified ad-

dress

• Automated on-chip erase algorithm

- Automatically preprograms/erases chip or specified

sectors

• Hardware RESET pin

- Resets internal state machine to read mode

• Low power consumption

- 200 nA typical automatic sleep mode current

- 200 nA typical standby current

- 10 mA typical read current

• JEDEC standard software, packages and pinouts

- 48-pin TSOP

- 44-pin SO

• Detection of program/erase cycle completion

- DQ7 DATA polling

- DQ6 toggle bit

- DQ2 toggle bit

- RY/BY output

• Erase suspend/resume

- Supports reading data from or programming data to a

sector not being erased

• Low V

write lock-out below 1.5V

• 10 year data retention at 150C

• 100,000 write/erase cycle endurance

Logic block diagram

RY/BY

RESET

Program/erase

control

Command

A-1

Program voltage

generator

Sector protect/

erase voltage

switches

Erase voltage

generator

DQ0–DQ15

Pin arrangement

48-pin TSOP

A15

A14

A13

A12

A11

A10

RESET

RY/BY

A18

A17

RY/BY

A18

A17

44-pin SO

RESET

A10

A11

A12

A13

A14

A15

A16

BYTE

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

Input/output

buffers

BYTE

AS29LV800

Chip enable

Output enable

Logic

STB

Data latch

DQ0

DQ8

DQ1

DQ9

DQ2

detector

Timer

Address latch

STB

Y decoder

Y gating

X decoder

Cell matrix

DQ10

DQ3

DQ11

A0–A18

A16

BYTE

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

Selection guide

29LV800-80

Maximum access time

Maximum chip enable access time

Maximum output enable access time

29LV800-90

29LV800-120

120

Unit

DID 11-40002-A. 10/19/00

ALLIANCE SEMICONDUCTOR

AS29LV800

AS29LV800

October 2000

Functional description

The AS29LV800 is an 8 megabit, 3.0 volt only Flash memory organized as 1 Megabyte of 8 bits/512Kbytes of 16 bits each.

For flexible erase and program capability, the 8 megabits of data is divided into nineteen sectors: one 16K, two 8K, one 32K,

and fifteen 64k byte sectors; or one 8K, two 4K, one 16K, and fifteen 32K word sectors. The ×8 data appears on DQ0–DQ7;

the ×16 data appears on DQ0–DQ15. The AS29LV800 is offered in JEDEC standard 48-pin TSOP and 44-pin SOP

packages. This device is designed to be programmed and erased in-system with a single 3.0V V

supply. The device can

also be reprogrammed in standard EPROM programmers.

The AS29LV800 offers access times of 80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To

eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls.

Word mode (×16 output) is selected by BYTE = high and Byte mode (×8 output) is selected by BYTE = low.

The AS29LV800 is fully compatible with the JEDEC single power supply Flash standard. Write commands to the command

register using standard microprocessor write timings. An internal state-machine uses register contents to control the erase

and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase

operations. Read data from the device in the same manner as other Flash or EPROM devices. Use the program command

sequence to invoke the automated on-chip programming algorithm that automatically times the program pulse widths and

verifies proper cell margin. Use the erase command sequence to invoke the automated on-chip erase algorithm that

preprograms the sector if it is not already programmed before executing the erase operation, times the erase pulse widths,

and verifies proper cell margin.

Boot sector architecture enables the system to boot from either the top (AS29LV800T) or the bottom (AS29LV800B) sector.

Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other

sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both program and

erase operations in all or any combination of the nineteen sectors. The device provides true background erase with Erase

Suspend, which puts erase operations on hold to either read data from or program data to a sector that is not being erased.

The chip erase command will automatically erase all unprotected sectors.

A factory shipped AS29LV800 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed

into the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0

to 1. Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on

other sectors.

The device features single 3.0V power supply operation for read, write, and erase functions. Internally generated and

regulated voltages are provided for the program and erase operations. A low V

detector automatically inhibits write

operations during power transtitions. The RY/BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect end

of program or erase operations. The device automatically resets to the read mode after program/erase operations are

completed. DQ2 indicates which sectors are being erased.

The AS29LV800 resists accidental erasure or spurious programming signals resulting from power transitions. Control

register architecture permits alteration of memory contents only after successful completion of specific command sequences.

During power up, the device is set to read mode with all program/erase commands disabled when V

is less than V

LKO

(lockout voltage). The command registers are not affected by noise pulses of less than 5 ns on OE, CE, or WE. To initiate

write commands, CE and WE must be logical zero and OE a logical one.

When the device’s hardware RESET pin is driven low, any program/erase operation in progress is terminated and the internal

state machine is reset to read mode. If the RESET pin is tied to the system reset circuitry and a system reset occurs during an

automated on-chip program/erase algorithm, data in address locations being operated on may become corrupted and requires

rewriting. Resetting the device enables the system’s microprocessor to read boot-up firmware from the Flash memory.

The AS29LV800 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are

programmed one at a time using EPROM programming mechanism of hot electron injection.

ALLIANCE SEMICONDUCTOR

DID 11-40002-A. 10/19/00

AS29LV800T-80TC Related Products

	AS29LV800T-80TC	AS29LV800	AS29LV800T-80TI
Description	3V 1M】8/512k】16 cmos flash eeprom	3V 1M】8/512k】16 cmos flash eeprom	3V 1M】8/512k】16 cmos flash eeprom

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