IS64VF12832A-7.5TQLA3 datasheet, PDF

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IS64VF12832A-7.5TQLA3: DescriptionCache SRAM, 128KX32, 7.5ns, CMOS, PQFP100, LEAD FREE, TQFP-100; Categorystorage storage; File Size516KB，25 Pages; ManufacturerIntegrated Silicon Solution ( ISSI ); Environmental Compliance

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IS64VF12832A-7.5TQLA3 Overview

Cache SRAM, 128KX32, 7.5ns, CMOS, PQFP100, LEAD FREE, TQFP-100

IS64VF12832A-7.5TQLA3 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	QFP
package instruction	LQFP, QFP100,.63X.87
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Factory Lead Time	12 weeks
Maximum access time	7.5 ns
Other features	FLOW-THROUGH ARCHITECTURE
Maximum clock frequency (fCLK)	117 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e3
length	20 mm
memory density	4194304 bit
Memory IC Type	CACHE SRAM
memory width	32
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
organize	128KX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	2.5 V
Certification status	Not Qualified
Filter level	AEC-Q100
Maximum seat height	1.6 mm
Maximum standby current	0.045 A
Minimum standby current	2.38 V
Maximum slew rate	0.175 mA
Maximum supply voltage (Vsup)	2.75 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	14 mm
Base Number Matches	1

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IS61(64)LF12832A IS64VF12832A

IS61(64)LF12836A IS61(64)VF12836A

IS61(64)LF25618A IS61(64)VF25618A

128K x 32, 128K x 36, 256K x 18

4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

FEBRUARY 2014

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth expan-

sion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• Power Supply

LF: V

3.3V + 5%,

ddq

3.3V/2.5V + 5%

VF: V

2.5V -5% +10%,

ddq

2.5V -5% +10%

• JEDEC 100-Pin QFP, 119-pin BGA, and 165-pin

BGA packages

• Automotive temperature available

• Lead-free available

LF/VF12836A and IS61(64)LF/VF25618A are high-speed,

low-power synchronous static RAMs designed to provide

burstable, high-performance memory for communication

and networking applications. The IS61(64)LF12832A is

organized as 131,072 words by 32 bits. The IS61(64)LF/

VF12836A is organized as 131,072 words by 36 bits. The

IS61(64)LF/VF25618A is organized as 262,144 words by

18 bits. Fabricated with

ISSI

's advanced CMOS technol-

ogy, the device integrates a 2-bit burst counter, high-speed

SRAM core, and high-drive capability outputs into a single

monolithic circuit. All synchronous inputs pass through

registers controlled by a positive-edge-triggered single

clock input.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be one

to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

Byte write operation is performed by using byte write en-

able (BWE) input combined with one or more individual

byte write signals (BWx). In addition, Global Write (GW)

is available for writing all bytes at one time, regardless of

the byte write controls.

Bursts can be initiated with either ADSP (Address Status

Processor) or

ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be gener-

ated internally and controlled by the

ADV (burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Interleave

burst is achieved when this pin is tied HIGH or left floating.

DESCRIPTION

The

ISSI

IS61(64)LF12832A, IS64VF12832A, IS61(64)

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

-6.5

6.5

7.5

133

-7.5

7.5

8.5

117

Units

MHz

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-

est version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-

ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications

unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.

Rev. G1

2/11/2014

IS64VF12832A-7.5TQLA3 Related Products

	IS64VF12832A-7.5TQLA3	IS64LF12836A-7.5B3LA3
Description	Cache SRAM, 128KX32, 7.5ns, CMOS, PQFP100, LEAD FREE, TQFP-100	Cache SRAM, 128KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, TFBGA-165
Is it Rohs certified?	conform to	conform to
Maker	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )
package instruction	LQFP, QFP100,.63X.87	TBGA, BGA165,11X15,40
Reach Compliance Code	compliant	compliant
Factory Lead Time	12 weeks	12 weeks
Maximum access time	7.5 ns	7.5 ns
Maximum clock frequency (fCLK)	117 MHz	117 MHz
I/O type	COMMON	COMMON
JESD-30 code	R-PQFP-G100	R-PBGA-B165
length	20 mm	15 mm
memory density	4194304 bit	4718592 bit
Memory IC Type	CACHE SRAM	CACHE SRAM
memory width	32	36
Number of functions	1	1
Number of terminals	100	165
word count	131072 words	131072 words
character code	128000	128000
Operating mode	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C
organize	128KX32	128KX36
Output characteristics	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	TBGA
Encapsulate equivalent code	QFP100,.63X.87	BGA165,11X15,40
Package shape	RECTANGULAR	RECTANGULAR
Package form	FLATPACK, LOW PROFILE	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL	PARALLEL
power supply	2.5 V	2.5/3.3,3.3 V
Certification status	Not Qualified	Not Qualified
Filter level	AEC-Q100	AEC-Q100
Maximum seat height	1.6 mm	1.2 mm
Maximum standby current	0.045 A	0.045 A
Minimum standby current	2.38 V	3.14 V
Maximum slew rate	0.175 mA	0.175 mA
Maximum supply voltage (Vsup)	2.75 V	3.465 V
Minimum supply voltage (Vsup)	2.375 V	3.135 V
Nominal supply voltage (Vsup)	2.5 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE
Terminal form	GULL WING	BALL
Terminal pitch	0.65 mm	1 mm
Terminal location	QUAD	BOTTOM
width	14 mm	13 mm

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