MT4DT232DM-6 datasheet, PDF - EEWORLD Datasheet

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MT4DT232DM-6: DescriptionFast Page DRAM Module, 2MX32, 60ns, CMOS, SIMM-72; Categorystorage storage; File Size341KB，21 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT4DT232DM-6 Overview

Fast Page DRAM Module, 2MX32, 60ns, CMOS, SIMM-72

MT4DT232DM-6 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Micron Technology
Parts packaging code	SIMM
package instruction	SIMM-72
Contacts	72
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FAST PAGE
Maximum access time	60 ns
Other features	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
Spare memory width	16
I/O type	COMMON
JESD-30 code	R-XSMA-N72
memory density	67108864 bit
Memory IC Type	FAST PAGE DRAM MODULE
memory width	32
Humidity sensitivity level	1
Number of functions	1
Number of ports	1
Number of terminals	72
word count	2097152 words
character code	2000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX32
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	SIMM
Encapsulate equivalent code	SSIM72
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Certification status	Not Qualified
refresh cycle	1024
Maximum seat height	20.574 mm
self refresh	NO
Maximum standby current	0.012 A
Maximum slew rate	0.352 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	SINGLE
Maximum time at peak reflow temperature	NOT SPECIFIED

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OBSOLETE

1, 2 MEG x 32

DRAM SIMMs

DRAM

MODULE

FEATURES

• JEDEC- and industry-standard pinout in a 72-pin,

single in-line memory module (SIMM)

• 4MB (1 Meg x 32) and 8MB (2 Meg x 32)

• High-performance CMOS silicon-gate process

• Single +5V

±10%

power supply

• All inputs, outputs and clocks are TTL-compatible

• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#

(CBR) and HIDDEN

• Multiple RAS# lines allow x16 or x32 width

• 1,024-cycle refresh distributed across 16ms

• FAST PAGE MODE (FPM) access or

Extended Data-Out (EDO) PAGE MODE access

MT2D(T)132(X)

MT4D(T)232D(X)

For the latest data sheet revisions, please refer to the Micron

Web site: www.micron.com/mti/msp/html/datasheet.html

PIN ASSIGNMENT (Front View)

72-Pin SIMM

1 Meg x 32 – TSOP version (shown)

1 Meg x 32 – SOJ version

2 Meg x 32 – TSOP version

2 Meg x 32 – SOJ version

OPTIONS

• Timing

50ns access

60ns access

• Components

SOJ

TSOP

• Packages

72 -pin SIMM

72 -pin SIMM (Gold)

• Operating Modes

FAST PAGE MODE

EDO PAGE MODE

**EDO version only

MARKING

-5**

-6

None

KEY TIMING PARAMETERS

EDO Operating Mode

SPEED

-5

-6

RAC

CAC

CAS

PIN SYMBOL

DQ1

DQ17

DQ2

DQ18

DQ3

DQ19

DQ4

DQ20

*4MB version only

PIN SYMBOL

NC (A10)

DQ5

DQ21

DQ6

CAS0#

DQ22

CAS2#

DQ7

CAS3#

DQ23

CAS1#

DQ8

RAS0#

DQ24

45 NC*/RAS1# 63

NC (A11)

WE#

DQ9

DQ25

33 NC*/RAS3# 51

DQ10

RAS2#

DQ26

DQ11

DQ27

SYMBOL

DQ12

DQ28

DQ13

DQ29

DQ30

DQ14

DQ31

DQ15

DQ32

DQ16

PRD1

PRD2

PRD3

PRD4

84ns

104ns

50ns

60ns

20ns

25ns

30ns

15ns

17ns

8ns

10ns

NOTE:

Symbols in parentheses are not used on these modules but may be used

for other modules in this product family. They are for reference only.

FPM Operating Mode

SPEED

-6

RAC

CAC

110ns

60ns

35ns

30ns

15ns

40ns

GENERAL DESCRIPTION

The MT2D(T)132(X) and MT4D(T)232D(X) are randomly

accessed, 4MB and 8MB solid-state memories organized in

a x32 configuration. During READ or WRITE cycles, each

1, 2 Meg x 32 SIMMs

DM57.p65 – Rev. 9/98

bit is uniquely addressed through 20 address bits that are

entered 10 bits (A0 -A9) at a time. RAS# is used to latch the

first 10 bits and CAS# the latter 10 bits. A READ or WRITE

cycle is selected with the WE# input. A logic HIGH on WE#

dictates read mode, while a logic LOW on WE# dictates

write mode. During a WRITE cycle, data-in (D) is latched by

the falling edge of WE# or CAS#, whichever occurs last.

EARLY WRITE occurs when WE# goes LOW prior to CAS#

going LOW, and the output pin(s) remain open (High-Z)

until the next CAS# cycle.

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Micron Technology, Inc.

Micron is a registered trademark of Micron Technology, Inc.

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