EPF10K20TI144-4 datasheet, PDF

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EPF10K20TI144-4: Descriptionfpga - field programmable gate array fpga - flex 10k 144 labs 102 ios; CategoryProgrammable logic devices Programmable logic; File Size2MB，128 Pages; ManufacturerAltera (Intel)

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EPF10K20TI144-4 Overview

fpga - field programmable gate array fpga - flex 10k 144 labs 102 ios

EPF10K20TI144-4 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Altera (Intel)
Parts packaging code	QFP
package instruction	TQFP-144
Contacts	144
Reach Compliance Code	unknown
ECCN code	EAR99
maximum clock frequency	294 MHz
JESD-30 code	S-PQFP-G144
JESD-609 code	e0
length	20 mm
Humidity sensitivity level	3
Dedicated input times	4
Number of I/O lines	102
Number of entries	102
Number of logical units	1152
Output times	102
Number of terminals	144
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4 DEDICATED INPUTS, 102 I/O
Output function	REGISTERED
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP144,.63SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	220
power supply	3.3/5,5 V
Programmable logic type	LOADABLE PLD
propagation delay	0.6 ns
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	20 mm

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Includes

FLEX 10KA

FLEX 10K

Embedded Programmable

Logic Device Family

Data Sheet

January 2003, ver. 4.2

Features...

■

The industry’s first embedded programmable logic device (PLD)

family, providing System-on-a-Programmable-Chip (SOPC)

integration

–

Embedded array for implementing megafunctions, such as

efficient memory and specialized logic functions

–

Logic array for general logic functions

High density

–

10,000 to 250,000 typical gates (see

Tables 1

and

–

Up to 40,960 RAM bits; 2,048 bits per embedded array block

(EAB), all of which can be used without reducing logic capacity

System-level features

–

MultiVolt

I/O interface support

–

5.0-V tolerant input pins in FLEX

10KA devices

–

Low power consumption (typical specification less than 0.5 mA

in standby mode for most devices)

–

FLEX 10K and FLEX 10KA devices support peripheral

component interconnect Special Interest Group (PCI SIG)

PCI

Local Bus Specification, Revision 2.2

–

FLEX 10KA devices include pull-up clamping diode, selectable

on a pin-by-pin basis for 3.3-V PCI compliance

–

Select FLEX 10KA devices support 5.0-V PCI buses with eight or

fewer loads

–

Built-in Joint Test Action Group (JTAG) boundary-scan test

(BST) circuitry compliant with IEEE Std. 1149.1-1990, available

without consuming any device logic

Table 1. FLEX 10K Device Features

Feature

Typical gates (logic and RAM)

(1)

Maximum system gates

Logic elements (LEs)

Logic array blocks (LABs)

Embedded array blocks (EABs)

Total RAM bits

Maximum user I/O pins

EPF10K10

EPF10K10A

10,000

31,000

576

6,144

150

EPF10K20

20,000

63,000

1,152

144

12,288

189

EPF10K30

EPF10K30A

30,000

69,000

1,728

216

12,288

246

EPF10K40

40,000

93,000

2,304

288

16,384

189

EPF10K50

EPF10K50V

50,000

116,000

2,880

360

20,480

310

Altera Corporation

DS-F10K-4.2

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