JL4-Series Specifications
8.89L x 7.37W x 4.32H (mm)
PDI Model
JL4-Series
provides precision timing in a hermetically
sealed package, and is available in both standard and custom frequencies
and configurations. PDI provides quick-turn sampling for your proto-typing
needs, mass production capability, and competitive pricing.
ex)
JL4—T—25000X—C—D—A—3—R—X
*
ENABLE
T
= Tri-State
N
= No/Connect
FREQUENCY
00030X-99999X
=
0.0300 MHz –
99.999 MHz
C10000-C20000
=
100.00 MHz –
200.00 MHz
OUTPUT
C
= TTL/CMOS
O
= LVCMOS
FREQUENCY
STABILITY
B
= ±25 **
C
= ±50
D
= ±100
S
= Special
OPERATING
TEMPERATURE
A
= 0 to +70°C
B
= -20 to +70°C
D
= -40 to +85°C
E
= -55 to +125°C
S
= Special
SUPPLY
VOLTAGE
1
= 1.8
2
= 2.5
F
= 3.0
3
= 3.3
PACKAGE
R
= Tape & Reel
** - Not available -55 to +125°C
* - for standard or assigned for customization.
Parameter
Frequency Range
Frequency Stability
*1
Temperature Range
*1
*1
Supply Voltage
*1
(±10%)
3.3
3.0
2.5
1.8
*2
Units
V
MHz
ppm
°C
°C
Supply Current (Maximum)
Output
Load
Duty Cycle (at 50% Vcc)
Rise/Fall Times (Maximum)
Start up Time (Maximum)
Output Voltage Levels
All Causes (Maximum )
Operating
Storage
0.030000 to 23.999999 MHz
24.000000 to 49.999999 MHz
50.000000 to 69.999999 MHz
70.000000 to 200.000000 MHz
15
20
30
45
Rise Time (10% to 90% Vcc)
Fall Time (90% to 10% Vcc)
High (Minimum)
Low (Maximum)
High (See below) or Open
Low (See below)
*3
High Value (Minimum)
Low Value (Maximum)
*3
Disable Current (Maximum)
*3
Enable Delay Time (Maximum)
Disable Delay Time (Maximum)
8
8
Pin 1 (Tri-State) (Option)
80
20
10
0.030000 to 200.0000
Per Option
Per Option
-55 to +125
15
15
20
20
30
30
45
45
Per Option
15pF/10 TTL gates
40 to 60% (45 to 55% option)
8
7
8
7
10
90
10
Enable
Disable
80
80
20
20
10
10
10
150
10
12
15
25
mA
6
6
ns
ms
% Vcc
80
20
10
% Vcc
% Vcc
uA
ms
ns
*1 - Not all Frequency/Temperature/Voltage combinations are available.
*2 - Inclusive of Tolerance @25°C, Operating Temperature, Supply Voltage, Load, Aging, Shock and Vibration.
*3 - Internal crystal oscillation halted.
REV:
NA
SIZE:
A
CAGE:
0S4G1
1
of
3
JL4-Series
8.89 x 7.37 x 4.32
(mm)
PA C K A G E D I M E N S I O N S
PIN
1
2
3
4
3
CONNECTION
Tri-State or No Connect
Ground/Case
Output
Supply Voltage
Decimal XXX = ± .008, XX = ± .02 Metric [XXX = ± .20], [XX = ± .50]
Top View:
.350 ±.005
[8.89 ±.13]
4
.290 ±.005
[7.37 ±.13]
PDI
Frequency
Date Code
2
FKA number
ESD Symbol
for Pin 1
.170 Max.
[4.32 Max.]
.004
C
Traceability Code
.315 Max.
[8.00 Max.]
Seating Plane
.018 ±.003
[.46 ±.08]
.200 ±.008
[5.08 ±.20]
.100
[2.54]
.030 R
[.76 R]
.240 ±.006
[6.10 ±.15]
.200
[5.08]
4
3
.125
[3.18]
.240
[6.10]
1
Bottom View:
2
.060
[1.52]
NOTES:
Other options are available, please consult factory.
All product is supplied
RoHS
and
REACH
compliant.
Product can be supplied on Tape and Reel, on reels of 1,000 units.
Specifications subject to change without notice, last updated 4/1/13.
REV:
NA
SIZE:
A
CAGE:
0S4G1
2
of
3
JL4-Series
8.89 x 7.37 x 4.32
(mm)
1.
Material: Black Conductive Polystyrene or equivalent.
2.
10 Sprocket Hole pitch cumulative tolerance of ±.008.
3.
Camber in compliance with EIA 481.
4.
Empty pockets: Trailing end (Minimum) 200 mm. and Leading end (Minimum) 400 mm.
5.
Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.
.012±.002
[0.30±.05]
Ø.059
[Ø1.50]
.157 Typ.
[4.00 Typ.]
.069
[1.75]
.079
[2.00]
A
.453
[11.50]
.945 ±.012
[24.00 ±.30]
Frequency
D/C
PDI XXXXX
Frequency
D/C
PDI XXXXX
Frequency
D/C
Section A-A
.630 Typ.
[16.00 Typ.]
A
120°
Ø13.000
[Ø330.00]
3.94
[100.00]
REV:
NA
SIZE:
A
CAGE:
0S4G1
3
of
3
FPGA/CPLD
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