DATASHEET
MOST
®
CLOCK INTERFACE
Description
The IDT5V80001 is a high performance clock interface for
use in MOST
®
(Media Oriented Systems Transport)
enabled systems. It can be used in two modes: generating
a master clock for the ring, or performing clock/data
recovery in a slave node.
IDT5V80001
Features
•
•
•
•
•
•
•
•
Packaged in 20-pin TSSOP
-40 to +85°C temperature range (industrial)
Compliant to AEC Q100
Operating voltage of 3.3 V
5 volt tolerant input for FOT
Low jitter generation
Power-down tri-state mode
Advanced, low-power CMOS process
Block Diagram
BYPASS
FOT_IN
1
Retiming
0
MUX
0
1
FOT_OUT
MOST_Din
RESET
CDR
PLL
INPUT_COPY
RCLK
X1
Crystal
Oscillator
X2
Master
PLL
MCLK
S1
S0
OEM
IDT™
MOST
®
CLOCK INTERFACE
1
IDT5V80001
REV S 083109
IDT5V80001
MOST
®
CLOCK INTERFACE
SYNTHESIZERS
Pin Assignment
X2
X1
RESET
VDD
FOT_OUT
GND
S1
FOT_IN
S0
LF
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
MOST_Din
INPUT_COPY
VDD
RCLK
GND
MCLK
OEM
BYPASS
LFR
Frequency Selection Tables
S1 S0
0
0
1
1
0
1
0
1
Operating
Frequency (RCLK)
45.1584 MHz
49.152 MHz
90.3168 MHz
98.304 MHz
Mode
MOST 25
MOST 25
MOST 50
MOST 50
Sampling
Frequency
44.1 kHz
48 kHz
44.1 kHz
48 kHz
OEM
0
1
MCLK Output
LOW
Running
Source for Retiming Block
RCLK (slave node)
MCLK (master node)
20-pin TSSOP
OEM
0
Node
Slave
Bypass
0
1
FOT_OUT
Retimed (RCLK) MOST_Din
*
FOT_IN
Retimed (MCLK) MOST_Din
FOT_IN
1
Master
0
1
*
FOT_IN must be present in order to generate RCLK and
Retimed (RCLK) MOST_Din.
Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
Name
X2
X1
RESET
VDD
FOT_OUT
GND
S1
FOT_IN
S0
Type
Input
Input
Input
Power
Output
Power
Input
Input
Input
Pin Description
Connect to 21.504 MHz crystal.
Connect to 21.504 MHz crystal.
Low to reset CDR PLL. Internal pull-up resistor.
Connect to 3.3 V supply.
Output for fiber optic MOST transceiver. 3.3 V LVTTL levels.
Connect to ground.
Frequency select input pin. See table above. No internal pull-up or pull-down
resistor.
Input to device from fiber optic MOST transceiver. 3.3 V LVTTL levels, 5 V
tolerant.
Frequency select input pin. See table above. No internal pull-up or pull-down
resistor.
IDT™
MOST
®
CLOCK INTERFACE
2
IDT5V80001
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IDT5V80001
MOST
®
CLOCK INTERFACE
SYNTHESIZERS
Pin
10
11
12
13
14
15
16
17
18
19
20
Name
LF
LFR
BYPASS
OEM
MCLK
GND
RCLK
VDD
INPUT_COPY
MOST_Din
NC
Type
Input
Input
Input
Input
Output
Power
Output
Power
Output
Input
—
Pin Description
Loop filter connection for CDR PLL.
Loop filter return. Connected to ground internally.
MUX control to bypass CDR PLL. Active high. No internal pull-up or pull-down
resistor.
High to enable MCLK. See table above. No internal pull-up or pull-down
resistor.
Master clock output. Clean clock derived from crystal. See table above. Weak
pull-down when OEM = 0.
Connect to ground.
Recovered clock out. See table above.
Connect to 3.3 V supply.
Retimed copy of FOT_IN input.
MOST data input.
No Connect. Do not connect this pin to anything.
Operation
The IDT5V80001 performs clock generation and recovery
for either a master or slave node in a MOST ring. It provides
a interface between a controller (typically implemented in an
ASIC or FPGA) and the fiber optic transceiver (FOT).
When used in a Master node (OEM = High), the Master PLL
synthesizes a frequency of twice the MOST data rate as the
MCLK output, and also reclocks the data from the controller
that is input on the FOT_IN pin to the INPUT_COPY output.
The output data on FOT_OUT is the MOST_Din data
retimed to MCLK if BYPASS is driven low, or the FOT_IN
data if BYPASS is driven high. Simultaneously, the device
recovers the clock from data on the FOT_IN pin and outputs
a 2x clock on RCLK.
In a slave node, OEM is set low and the MCLK output is
disabled. Data from the controller (FOT_IN) is retimed using
the recovered clock and output on the INPUT_COPY. If
BYPASS is driven high, the controller data (FOT_IN) is also
transmitted on the FOT_OUT output but is not retimed to
RCLK. If BYPASS is driven low, the MOST_Din data is
retimed and transmitted on the FOT_OUT output.
To recover the clock from the data stream, the two PLLs
work together. The lock sequence from power on is:
1.
Crystal oscillator starts and stabilizes.
2.
Master (frequency synthesis) PLL starts and locks to the
crystal.
3.
CDR PLL starts and locks to the master PLL to obtain a
frequency operation point.
4.
Activity is detected on FOT_IN.
5.
CDR PLL phase-locks to incoming data.
Extreme conditions, such as electrical transients, phase
steps or brief dropouts on the FOT_IN pin may cause the
CDR PLL to unlock. If this occurs and the controller begins
to experience data errors, it should set RESET low for at
least 50 ns to restart the data lock sequence from step 3.
IDT™
MOST
®
CLOCK INTERFACE
3
IDT5V80001
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IDT5V80001
MOST
®
CLOCK INTERFACE
SYNTHESIZERS
External Components
The IDT5V80001 requires a minimum number of external
components for proper operation.
The nominal impedance of the clock output is 20
Ω
.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between each VDD pins and the ground plane, as close to
these pins as possible. For optimum device performance,
the decoupling capacitor should be mounted on the
component side of the PCB.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitors should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
2) The external crystal should be mounted just next to the
device with short traces.
3) The external loop filter components should be mounted
close to the IDT5V80001 and away from digital signals,
switching power supply components, and other sources of
noise.
4) To minimize EMI, 33
Ω
series termination resistors should
be placed close to the clock outputs.
5) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
IDT5V80001. This includes signal traces just underneath
the device, or on layers adjacent to the ground plane layer
used by the device.
External Loop Filter
Crystal
The IDT5V80001 requires a 21.504 MHz parallel resonant
crystal. Recommended devices are:
Manufacturer
Abracon
NDK
Package
5x7 mm ceramic
Part #
AAH-363-21.504MHz
3.2x5 mm ceramic EXS00A-CG00294
Crystal Load Capacitors
The device crystal connections should include pads for
capacitors from X1 to ground and from X2 to ground. These
capacitors are used to adjust the stray capacitance of the
board to match the nominally required crystal load
capacitance.
The value (in pF) of these crystal caps should equal (C
L
-12
pF)*2. In this equation, C
L
= crystal load capacitance in pF.
For the specified 16 pF load capacitance, each crystal
capacitor would be 8 pF [(16-12) x 2 = 8].
External Loop Filter
An external loop filter is required for operation of the CDR
PLL. Recommended components are:
R
S
= 1210
Ω
1% tolerance
,
C
S
= 10 nF, use capacitor with a non-piezoelectric dielectric.
Recommended type is Panasonic ECH-U01103GX5 or
equivalent.
9
LF
10
12
11
LFR
Series Termination Resistor
Termination should be used on the FOT_OUT, MCLK,
RCLK, and INPUT_COPY output (pins 5, 14, 16, and 18
respectively). To series terminate a 50
Ω
trace (a commonly
used trace impedance) place a 33
Ω
resistor in series with
the clock line, as close to the clock output pin as possible.
R
S
C
S
IDT™
MOST
®
CLOCK INTERFACE
4
IDT5V80001
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IDT5V80001
MOST
®
CLOCK INTERFACE
SYNTHESIZERS
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5V80001. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
Inputs and Outputs
Input (FOT_IN only)
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
7V
-65 to +150° C
125° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured with respect to GND)
Power Supply Ramp Time
Min.
-40
+3.0
Typ.
+3.3V
Max.
+85
+3.6
4
Units
°
C
V
ms
IDT™
MOST
®
CLOCK INTERFACE
5
IDT5V80001
REV S 083109
Switching Power Supply Study Group
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