W162
Spread Aware™, Zero Delay Buffer
Features
• Spread Aware™—designed to work with SSFTG
reference signals
• Two banks of four outputs, plus the fed back output
• Outputs may be three-stated
• Available in 16-pin SOIC or SSOP package
• Extra strength output drive available (-19 version)
• Internal feedback
Table 1. Input Logic
SEL1
0
0
1
1
SEL0
0
1
0
1
QA0:3
Three-
State
Active
Active
Active
QB0:3
Three-
State
Three-
State
Active
Active
PLL
Shutdown
Active,
Utilized
Shutdown,
Bypassed
Active,
Utilized
QFB
Active
Active
Active
Active
Key Specifications
Operating Voltage: ............................................... 3.3V±10%
Operating Range: ................................15 < f
OUT
< 133 MHz
Cycle-to-Cycle Jitter: .................................................. 250 ps
Output to Output Skew: ............................................. 150 ps
Propagation Delay: ..................................................... 150 ps
Block Diagram
Pin Configuration
QFB
REF
PLL
REF
MUX
QA0
QA1
QA2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
QFB
QA3
QA2
VDD
GND
QB3
QB2
SEL0
QA0
QA1
VDD
GND
QB0
QA3
QB0
SEL0
QB1
SEL1
SEL1
QB1
QB2
QB3
Spread Aware is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
Document #: 38-07150 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 14, 02
W162
Pin Definitions
Pin Name
REF
QFB
QA0:3
QB0:3
VDD
GND
SEL0:1
Pin No.
1
16
2, 3, 14, 15
6, 7, 10, 11
4, 13
5, 12
9, 8
Pin
Type
I
O
O
O
P
P
I
Pin Description
Reference Input:
The output signals QA0:3 through QB0:3 will be synchro-
nized to this signal unless the device is programmed to bypass the PLL.
Feedback Output:
This signal is used as the feedback internally to establish
the propagation delay of nearly 0.
Outputs from Bank A:
The frequency of the signals provided by these pins
is equal to the signal connected to REF.
Outputs from Bank B:
The frequency of the signals provided by these pins
is equal to the signal connected to REF.
Power Connections:
Connect to 3.3V. Use ferrite beads to help reduce noise
for optimal jitter performance.
Ground Connections:
Connect all grounds to the common system ground
plane.
Function Select Inputs:
Tie to V
DD
(HIGH, 1) or GND (LOW, 0) as desired
per
Table 1.
For more details on Spread Spectrum timing technology,
please see the Cypress Application note titled, “EMI Suppres-
sion Techniques with Spread Spectrum Frequency Timing
Generator (SSFTG) ICs.”
Overview
The W162 products are nine-output zero delay buffers. A
Phase-Locked Loop (PLL) is used to take a time-varying signal
and provide eight copies of that same signal out.
Internal feedback is used to maximize the number of output
signals provided in the 16-pin package.
Functional Description
Logic inputs provide the user the ability to turn off one or both
banks of clocks when not in use, as described in
Table 1.
Dis-
abling a bank of unused outputs will reduce jitter and power
consumption, and will also reduce the amount of EMI gener-
ated by the W162.
These same inputs allow the user to bypass the PLL entirely
if so desired. When this is done, the device no longer acts as
a zero delay buffer, it simply reverts to a standard nine-output
clock driver.
Spread Aware
Many systems being designed now utilize a technology called
Spread Spectrum Frequency Timing Generation. Cypress has
been one of the pioneers of SSFTG development, and we de-
signed this product so as not to filter off the Spread Spectrum
feature of the Reference input, assuming it exists. When a
zero delay buffer is not designed to pass the SS feature
through, the result is a significant amount of tracking skew
which may cause problems in systems requiring synchroniza-
tion.
Document #: 38-07150 Rev. *A
Page 2 of 7
W162
Absolute Maximum Ratings
[1]
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
.
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability
Rating
–0.5 to +7.0
–65 to +150
0 to +70
–55 to +125
0.5
Unit
V
°C
°C
°C
W
Parameter
V
DD
, V
IN
T
STG
T
A
T
B
P
D
Description
Voltage on any pin with respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Power Dissipation
DC Electrical Characteristics
:
T
A
=0°C to 70°C, V
DD
= 3.3V ±10%
Parameter
I
DD
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
Description
Supply Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
I
OL
= 12 mA (-19)
I
OL
= 8 mA (-9)
I
OL
= 12 mA (-19)
I
OL
= 8 mA (-9)
V
IN
= 0V
V
IN
= V
DD
2.4
–500
10
2.0
0.4
Test Condition
Unloaded, 100 MHz
Min
Typ
Max
40
0.8
Unit
mA
V
V
V
V
µA
µA
AC Electrical Characteristics:
T
A
= 0°C to +70°C, V
DD
= 3.3V ±10%
Parameter
f
IN
f
OUT
t
R
t
F
t
PD
t
SK
t
D
t
LOCK
t
JC
Description
Input Frequency
Output Frequency
Output Rise Time (-09)
[2]
Output Rise Time (-19)
[2]
Output Fall Time (-09)
[2]
Output Rise Time (-19)
[2]
FBIN to REF Skew
[3, 4]
Output to Output Skew
Duty Cycle
PLL Lock Time
Jitter, Cycle-to-Cycle
15-pF load
[6]
2.0 to 0.8V, 15-pF load
2.0 to 0.8V, 20-pF load
2.0 to 0.8V, 15-pF load
2.0 to 0.8V, 20-pF load
Measured at V
DD
/2
All outputs loaded equally
15-pF load
[5]
Power supply stable
45
50
2
Test Condition
Min
15
15
2
Typ
Max
133
133
2.5
1.5
2.5
1.5
150
150
55
1.0
250
Unit
MHz
MHz
ns
ns
ns
ns
ps
ps
%
ms
ps
Notes:
1.
Multiple Supplies:
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
2. Long input rise and fall time will degrade skew and jitter performance.
3. All AC specifications are measured with a 50
Ω
transmission line, load terminated with 50
Ω
to 1.4V.
4. Skew is measured at V
DD
/2 on rising edges.
5. Duty cycle is measured at V
DD
/2
6. For the higher drive -19, the load is 20 pF.
Document #: 38-07150 Rev. *A
Page 3 of 7
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