P2TC
www.vishay.com
Vishay Sfernice
High Precision Wraparound - ± 2 ppm/°C TCR
Thin Film Chip Resistors
FEATURES
• Load life stability 0.05 % typical at 2000 h
at 70 °C under Pn
• Low temperature coefficient:
± 2 ppm/°C
(-55 °C; +155 °C)
• Very low noise < - 35 dB and voltage coefficient
< 0.01 ppm/V
• Wide resistance range: 100
to 3.6 M
depending on size
DESIGN SUPPORT TOOLS AVAILABLE
D
D
3
3
3D Models
• Tolerances to
± 0.01 %
• Termination: thin film technology
• Sulfur resistant (per ASTM B809-95 humid vapor test)
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
For low noise and precision applications, superior stability,
low temperature coefficient of resistance, and low voltage
coefficient, Vishay Sfernice’s proven precision thin film
wraparound
resistors
exceed
requirements
of
MIL-PRF-55342G characteristics typical ± 2 ppm/°C
(-55 °C; +155 °C).
STANDARD ELECTRICAL SPECIFICATIONS
MODEL
SIZE
RESISTANCE
RANGE
()
100 to 88K
100 to 160K
100 to 360K
100 to 1.3M
100 to 3.6M
RATED
POWER
W
Pn
(1)
0.063
0.125
0.200
0.330
1
RATED
POWER
W
Pd
(1)
0.040
0.100
0.125
0.250
0.500
LIMITING
ELEMENT
VOLTAGE
V
50
75
150
200
300
TOLERANCE
±%
0.01, 0.02, 0.05, 0.1, 0.25, 0.5, 1, 2, 5
0.01, 0.02, 0.05, 0.1, 0.25, 0.5, 1, 2, 5
0.01, 0.02, 0.05, 0.1, 0.25, 0.5, 1, 2, 5
0.01, 0.02, 0.05, 0.1, 0.25, 0.5, 1, 2, 5
0.01, 0.02, 0.05, 0.1, 0.25, 0.5, 1, 2, 5
P2TC0402
P2TC0603
P2TC0805
P2TC1206
P2TC2010
0402
0603
0805
1206
2010
Notes
(1)
Pn = nominal power : Pd = derated power intended to improve stability
(2)
For ohmic range versus tolerance and TCR see detailed table on next page
CLIMATIC SPECIFICATIONS
Operating temperature
range
-55 °C; +155 °C
MECHANICAL SPECIFICATIONS
Substrate
Technology
Alumina
Thin film
Nickel chromium
with mineral
Note
• For temperature up to 230 °C, see PHT datasheet
(www.vishay.com/doc?53050)
Film
Protection
passivation
Epoxy + silicone
N type:
SnAg over nickel barrier for
PERFORMANCE VS. HUMID SULFUR VAPOR
Test conditions
Test results
50 °C ± 2 °C, 85 % ± 4 % RH,
exposure time 500 h
Resistance drift < (0.05 %
R
+ 0.05
),
no corrosion products observed
Terminations
solder reflow
G type:
gold over nickel barrier for
other applications
Revision: 29-Jul-2019
Document Number: 53080
1
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
P2TC
www.vishay.com
Vishay Sfernice
DIMENSIONS
in millimeters (inches)
A
D
D
C
B
E
E
CASE SIZE
0402
0603
0805
1206
2010
A
MAX. TOL.
+0.152 (+0.006)
MIN. TOL.
-0.152 (-0.006)
NOMINAL
1.00 (0.039)
1.52 (0.060)
1.91 (0.075)
3.06 (0.120)
5.08 (0.200)
B
MAX. TOL.
+0.127 (+0.005)
MIN. TOL.
-0.127 (-0.005)
NOMINAL
0.60 (0.024)
0.85 (0.033)
1.27 (0.050)
1.60 (0.063)
2.54 (0.100)
C
NOMINAL
0.25 (0.010)
0.5 (0.02)
± 0.127 (0.005)
0.38 (0.015)
0.40 (0.016)
0.48 (0.019)
D/E
TOLERANCE
0.1 (0.004)
0.13 (0.005)
SUGGESTED LAND PATTERN
(to IPC-7351A)
G
min.
X
max.
Z
max.
CHIP SIZE
0402
0603
0805
1206
2010
Z
max.
1.55 (0.061)
2.37 (0.093)
2.76 (0.109)
3.91 (0.154)
5.93 (0.233)
DIMENSIONS
in millimeters (inches)
G
min.
0.15 (0.006)
0.35 (0.014)
0.74 (0.029)
1.85 (0.073)
3.71 (0.146)
X
max.
0.73 (0.029)
0.98 (0.039)
1.40 (0.055)
1.73 (0.068)
2.67 (0.105)
TEMPERATURE COEFFICIENT
TYPICAL TCR
(ppm/°C)
±2
TYPICAL TCR AND MAX. SPREAD
(ppm/°C)
±2±2
POWER DERATING CURVE
Axis Title
120
100
2nd line
Rated Power (%)
80
60
40
20
0
0
20
40
60 70 80
100 120 140 160
155
Ambient Temperature (°C)
10
100
1000
1st line
2nd line
10000
Revision: 29-Jul-2019
Document Number: 53080
2
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
P2TC
www.vishay.com
Vishay Sfernice
RANGE
()
100 to < 250
250 to 88K
100 to < 250
250 to 160K
100 to < 250
250 to 360K
100 to < 250
250 to 1M3
100 to < 250
250 to 3M6
TOLERANCE
(± %)
0.02; 0.05; 0.1; 0.25; 0.5; 1; 2; 5
0.01; 0.02; 0.05; 0.1; 0.25; 0.5; 1; 2; 5
0.02; 0.05; 0.1; 0.25; 0.5; 1; 2; 5
0.01; 0.02; 0.05; 0.1; 0.25; 0.5; 1; 2; 5
0.02; 0.05; 0.1; 0.25; 0.5; 1; 2; 5
0.01; 0.02; 0.05; 0.1; 0.25; 0.5; 1; 2; 5
0.02; 0.05; 0.1; 0.25; 0.5; 1; 2; 5
0.01; 0.02; 0.05; 0.1; 0.25; 0.5; 1; 2; 5
0.02; 0.05; 0.1; 0.25; 0.5; 1; 2; 5
0.01; 0.02; 0.05; 0.1; 0.25; 0.5; 1; 2; 5
BEST TOLERANCE AND TCR VS. OHMIC VALUE
STYLE
0402
0603
0805
1206
2010
POPULAR OPTIONS
For any option it is recommended to consult Vishay Sfernice for availability first.
Option: Enlarged Terminations
For stringent and special power dissipation requirements, the thermal resistance between the resistive layer and the solder joint
can be reduced using enlarged terminations chip resistors which are soldered on large and thick copper pads acting as heatsink
(see application note: 53048 Power Dissipation in High Precision Vishay Sfernice Chip Resistors and Arrays (P Thin Film, PRA
Arrays, CHP Thick Film)
www.vishay.com/doc?53048.
Option to order 0063: (applies to size 1206 / 2010).
DIMENSIONS
(Option 0063) in millimeters
Bottom view for mounting
A
Uncoatted
ceramic
Enlarged
termination
B
D
F
D
E
E
CASE SIZE
1206
2010
A
MAX. TOL.
+0.152
MIN. TOL.
-0.152
NOMINAL
3.06
5.08
B
MAX. TOL.
+0.127
MIN. TOL.
-0.127
NOMINAL
1.60
2.54
E
MAX. TOL.
+0.13
MIN. TOL.
-0.13
NOMINAL
0.40
0.48
D
MAX. TOL.
+0.13
MIN. TOL.
-0.13
NOMINAL
1.215
2.215
F
NOMINAL
0.63
MIN.
0.50
MAX.
0.76
SUGGESTED LAND PATTERN
(Option 0063)
G
min.
X
max.
Z
max.
CHIP SIZE
1206
2010
Z
max.
3.91
5.93
DIMENSIONS (IN MILLIMETER)
G
min.
0.50
X
max.
1.73
2.67
Revision: 29-Jul-2019
Document Number: 53080
3
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
P2TC
www.vishay.com
Option: Marking
Option to order 0013:
Marking of ohmic value and tolerance:
Sizes: 0805 to 1005: 3 digits marking (according to EIA-96)
Sizes: 1206 to 2512: 4 digits marking (same codification than in the ordering procedure)
Tolerance indicated by a color dot.
Option to order 0014:
Marking of ohmic value:
Sizes: 0805 to 1005: 3 digits marking (according to EIA-96)
Sizes: 1206 to 2512: 4 digits marking (same codification than in the ordering procedure)
No standard marking available for smaller sizes.
A price adder will apply to the unit price of the parts for options 0013 and 0014.
Option: AEC-Q200
For moisture resistance test only.
Option to Order 0058:
Specific production process to withstand 85 °C/85 % at Pn/10
Vishay Sfernice
PACKAGING
ESD packaging available: waffle-pack, and plastic tape and
reel (low conductivity).
NUMBER OF PIECES PER PACKAGE
SIZE MOQ
WAFFLE PACK
2" × 2"
TAPE AND REEL
MIN.
MAX.
5000
100
0805
100
1206
2010
140
60
1000
100
4000
8 mm
TAPE
WIDTH
PACKAGING RULES
Waffle Pack
Can be filled up to maximum quantity indicated in the table
here above, taking into account the minimum order quantity.
When quantity ordered exceeds maximum quantity of a
single waffle pack, the waffle packs are stacked up on the
top of each other and closed by one single cover.
To get “not stacked up” waffle pack in case of ordered
quantity > maximum number of pieces per package:
Please consult Vishay Sfernice for specific ordering
code.
Tape and Reel
See Part Numbering information to get the quantity desired
by tape.
0603
PERFORMANCE
TESTS
Thermal shock
Short time overload
Low temperature operation
Resistance to solder heat
CONDITIONS
MIL-PRF-55342G
MIL-STD-202 F-Method 107 F
MIL-PRF-55342G
PARA 3.10.4.7.5
MIL-PRF-55342G
PARA 3.9 and 4.7.4
MIL-PRF-55342G
PARA 3.12, 4.7.7, 4.7.1.2
MIL-PRF-55342G
PARA 3.13 and 4.7.8
MIL-STD-202 F-Method 106 E
CECC 56 days / 40 °C / 93 % RH
High temperature
MIL-PRF-55342G
PARA 3.11 and 4.7.6
MIL-PRF-55342G
8000 h Pn at 70 °C
MIL-STD-202 F-Method 108 A
MIL OR CECC
REQUIREMENTS
± 0.05 %
± 0.05 %
± 0.05 %
± 0.05 %
TYPICAL
PERFORMANCES
± 0.02 %
± 0.01 %
± 0.01 %
± 0.03 %
± 0.10 %
± 0.10 %
± 0.05 %
± 0.01 %
± 0.01 %
± 0.05 %
Moisture resistance
Load life
± 0.5 %
± 0.1 %
(2)
Revision: 29-Jul-2019
Document Number: 53080
4
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
P2TC
www.vishay.com
Maximum permissible pulse load
P
i
max. for single pulse
(1)
Axis Title
100
2nd line
P
- Permissible Pulse Power (W)
10000
Vishay Sfernice
P2TC1206
10
P2TC2010
1000
1st line
2nd line
P2TC0402
1
P2TC0603
P2TC0805
100
0.1
0.00001
10
0.0001
0.001
0.01
t - Pulse Duration (s)
0.1
1
10
Energy for single pulse
(1)
Axis Title
100
10
2nd line
Permissible Pulse Energy (J)
1
P2TC1206
P2TC2010
10000
1000
P2TC0402
0.1
0.01
P2TC0805
P2TC0603
0.001
0.0001
100
0.00001
0.00001
10
0.0001
0.001
0.01
t - Pulse Duration (s)
0.1
1
10
Maximum permissible pulse voltage
U
i
max. for single pulse
(1)
Axis Title
10 000
10000
2nd line
Permissible Pulse Voltage (V)
1000
P2TC1206
P2TC2010
1000
1st line
2nd line
100
P2TC0402
P2TC0603
P2TC0805
100
10
0.00001
10
0.0001
0.001
0.01
t - Pulse Duration (s)
0.1
1
10
Note
(1)
One should apply the datas mentioned on the 3 curves together to get the right performances
Revision: 29-Jul-2019
Document Number: 53080
5
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
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2nd line
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