CS61884
Octal T1/E1/J1 Line Interface Unit
Features
Industry Standard Footprint
Octal E1/T1/J1 Short-haul Line Interface Unit
Low Power
No External Component Changes for
100
Ω/120 Ω/75 Ω
Operation
Pulse Shapes can be customized by the user
Internal AMI, B8ZS, or HDB3 Encoding/Decoding
LOS Detection per T1.231, ITU G.775, ETSI 300-233
G.772 Non-Intrusive Monitoring
G.703 BITS Clock Recovery
Crystal-less Jitter Attenuation
Serial/Parallel Microprocessor Control Interfaces
Transmitter Short Circuit Current Limiter (<50mA)
TX Drivers with Fast High-Z and Power Down
JTAG Boundary Scan compliant to IEEE 1149.1
144-Pin LQFP or 160-Pin BGA Package
ORDERING INFORMATION
CS61884-IQ
CS61884-IB
144-pin LQFP
160-pin FBGA
Description
The CS61884 is a full-featured Octal E1/T1/J1 short-
haul LIU that supports both 1.544 Mbps or 2.048 Mbps
data transmission. Each channel provides crystal-less
jitter attenuation that complies with the most stringent
standards. Each channel also provides internal
AMI/B8ZS/HDB3 encoding/decoding. To support en-
hanced system diagnostics, channel zero can be
configured for G.772 non-intrusive monitoring of any of
the other 7 channels’ receive or transmit paths.
The CS61884 makes use of ultra low power matched im-
pedance transmitters and receivers to reduce power
beyond that achieved by traditional driver designs. By
achieving a more precise line match, this technique also
provides superior return loss characteristics. Additional-
ly, the internal line matching circuitry reduces the
external component count. All transmitters have controls
for independent power down and High-Z.
Each receiver provides reliable data recovery with over
12 dB of cable attenuation. The receiver also incorpo-
rates LOS detection compliant to the most recent
specifications.
Note: Click on any
text
in blue to go to cross-references.
LOS
RCLK
RPOS
RNEG
TCLK
TPOS
TNEG
LOS
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Receiver
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Clock
Data
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Recovery
Recovery
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Jitter
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Attenuator
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Driver
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Transmit
Pulse
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Control
Shaper
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Decoder
Encoder
Remote Loopback
Analog Loopback
Digital Loopback
7
JTAG
Serial
Port
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
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JTAG Interface
Host Interface
RTIP
RRING
G.772 Monitor
TTIP
TRING
Host
Serial/Parallel
Port
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2002
(All Rights Reserved)
MAY ‘02
DS485PP4
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©
CS61884
TABLE OF CONTENTS
1. PINOUT - LQFP ........................................................................................................................................ 7
2. PINOUT - FBGA ........................................................................................................................................ 8
3. PIN DESCRIPTIONS ................................................................................................................................. 9
3.1 Power Supplies .................................................................................................................................. 9
3.2 Control .............................................................................................................................................. 10
3.3 Address Inputs/Loopbacks ............................................................................................................... 14
3.4 Cable Select ..................................................................................................................................... 15
3.5 Status ............................................................................................................................................... 15
3.6 Digital Rx/Tx Data I/O ....................................................................................................................... 16
3.7 Analog RX/TX Data I/O .................................................................................................................... 19
3.8 JTAG Test Interface ......................................................................................................................... 21
3.9 Miscellaneous ................................................................................................................................... 21
4. OPERATION ........................................................................................................................................... 22
5. POWER-UP ............................................................................................................................................. 22
6. MASTER CLOCK .................................................................................................................................... 22
7. G.772 MONITORING ............................................................................................................................... 22
8. BUILDING INTEGRATED TIMING SYSTEMS (BITS) CLOCK MODE .................................................. 23
9. TRANSMITTER ....................................................................................................................................... 24
9.1 Bipolar Mode .................................................................................................................................... 25
9.2 Unipolar Mode .................................................................................................................................. 25
9.3 RZ Mode ........................................................................................................................................... 25
9.4 Transmitter Powerdown / High-Z ...................................................................................................... 25
9.5 Transmit All Ones (TAOS) ................................................................................................................ 25
9.6 Automatic TAOS ............................................................................................................................... 26
9.7 Driver Failure Monitor ....................................................................................................................... 26
9.8 Driver Short Circuit Protection .......................................................................................................... 26
10. RECEIVER ............................................................................................................................................ 26
10.1 Bipolar Output Mode ...................................................................................................................... 26
10.2 Unipolar Output Mode .................................................................................................................... 26
10.3 RZ Output Mode ............................................................................................................................. 27
10.4 Receiver Powerdown/High-Z .......................................................................................................... 27
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product infor-
mation describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the infor-
mation contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this
information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus
and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only
for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying
for general distribution, advertising or promotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this ma-
terial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign
Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANT-
ED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade-
marks or service marks of their respective owners.
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CS61884
10.5 Loss-of-Signal (LOS) .......................................................................................................................27
10.6 Alarm Indication Signal (AIS) ..........................................................................................................28
JITTER ATTENUATOR .........................................................................................................................28
OPERATIONAL SUMMARY ..................................................................................................................29
12.1 Loopbacks .......................................................................................................................................29
12.2 Analog Loopback ............................................................................................................................29
12.3 Digital Loopback ..............................................................................................................................30
12.4 Remote Loopback ...........................................................................................................................30
HOST MODE ..........................................................................................................................................32
13.1 SOFTWARE RESET .......................................................................................................................32
13.2 Serial Port Operation .......................................................................................................................32
13.3 Parallel Port Operation ....................................................................................................................33
13.4 Register Set ....................................................................................................................................34
REGISTER DESCRIPTIONS .................................................................................................................35
14.1 Revision/IDcode Register (00h) ......................................................................................................35
14.2 Analog Loopback Register (01h) .....................................................................................................35
14.3 Remote Loopback Register (02h) ...................................................................................................35
14.4 TAOS Enable Register (03h) ..........................................................................................................35
14.5 LOS Status Register (04h) ..............................................................................................................35
14.6 DFM Status Register (05h) .............................................................................................................35
14.7 LOS Interrupt Enable Register (06h) ...............................................................................................36
14.8 DFM Interrupt Enable Register (07h) ..............................................................................................36
14.9 LOS Interrupt Status Register (08h) ................................................................................................36
14.10 DFM Interrupt Status Register (09h) .............................................................................................36
14.11 Software Reset Register (0Ah) .....................................................................................................36
14.12 Performance Monitor Register (0Bh) ............................................................................................36
14.13 Digital Loopback Reset Register (0Ch) .........................................................................................37
14.14 LOS/AIS Mode Enable Register (0Dh) ..........................................................................................37
14.15 Automatic TAOS Register (0Eh) ...................................................................................................37
14.16 Global Control Register (0Fh) .......................................................................................................38
14.17 Line Length Channel ID Register (10h) .........................................................................................38
14.18 Line Length Data Register (11h) ...................................................................................................39
14.19 Output Disable Register (12h) .......................................................................................................39
14.20 AIS Status Register (13h) .............................................................................................................39
14.21 AIS Interrupt Enable Register (14h) ..............................................................................................39
14.22 AIS Interrupt Status Register (15h) ...............................................................................................40
14.23 AWG Broadcast Register (16h) .....................................................................................................40
14.24 AWG Phase Address Register (17h) ............................................................................................40
14.25 AWG Phase Data Register (18h) ..................................................................................................40
14.26 AWG Enable Register (19h) ..........................................................................................................40
14.27 AWG Overflow Interrupt Enable Register (1Ah) ............................................................................41
14.28 AWG Overflow Interrupt Status Register (1Bh) .............................................................................41
14.29 JA Error Interrupt Enable Register (1Ch) ......................................................................................41
14.30 JA Error Interrupt Status Register (1Dh) .......................................................................................41
14.31 Bits Clock Enable Register (1Eh) ..................................................................................................41
14.32 Reserved Register (1Fh) ...............................................................................................................41
14.33 Status Registers ............................................................................................................................42
14.33.1 Interrupt Enable Registers ...................................................................................................42
14.33.2 Interrupt Status Registers ....................................................................................................42
ARBITRARY WAVEFORM GENERATOR ............................................................................................43
JTAG SUPPORT ....................................................................................................................................45
16.1 TAP Controller .................................................................................................................................45
16.1.1 JTAG Reset ...........................................................................................................................45
11.
12.
13.
14.
15.
16.
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CS61884
16.1.2 Test-Logic-Reset ................................................................................................................... 45
16.1.3 Run-Test-Idle ........................................................................................................................ 45
16.1.4 Select-DR-Scan .................................................................................................................... 46
16.1.5 Capture-DR ........................................................................................................................... 46
16.1.6 Shift-DR ................................................................................................................................ 46
16.1.7 Exit1-DR ................................................................................................................................ 46
16.1.8 Pause-DR ............................................................................................................................. 46
16.1.9 Exit2-DR ................................................................................................................................ 46
16.1.10 Update-DR .......................................................................................................................... 46
16.1.11 Select-IR-Scan .................................................................................................................... 47
16.1.12 Capture-IR .......................................................................................................................... 47
16.1.13 Shift-IR ................................................................................................................................ 47
16.1.14 Exit1-IR ............................................................................................................................... 47
16.1.15 Pause-IR ............................................................................................................................. 47
16.1.16 Exit2-IR ............................................................................................................................... 47
16.1.17 Update-IR ........................................................................................................................... 47
16.2 Instruction Register (IR) ................................................................................................................. 47
16.2.1 EXTEST ................................................................................................................................ 47
16.2.2 SAMPLE/PRELOAD ............................................................................................................. 47
16.2.3 IDCODE ................................................................................................................................ 47
16.2.4 BYPASS ............................................................................................................................... 47
16.3 Device ID Register (IDR) ................................................................................................................ 48
BOUNDARY SCAN REGISTER (BSR) ................................................................................................ 48
APPLICATIONS .................................................................................................................................... 51
18.1 Transformer specifications ............................................................................................................. 53
18.2 Crystal Oscillator Specifications ..................................................................................................... 53
18.3 Designing for AT&T 62411 ............................................................................................................. 53
18.4 Line Protection ............................................................................................................................... 53
CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 54
19.1 Absolute Maximum Ratings ............................................................................................................ 54
19.2 Recommended Operating Conditions ............................................................................................ 54
19.3 Digital Characteristics ..................................................................................................................... 55
19.4 Transmitter Analog Characteristics ................................................................................................ 55
19.5 Receiver Analog Characteristics .................................................................................................... 56
19.6 Jitter Attenuator Characteristics ..................................................................................................... 57
19.7 Master Clock Switching Characteristics ......................................................................................... 59
19.8 Transmit Switching Characteristics ................................................................................................ 59
19.9 Receive Switching Characteristics ................................................................................................. 59
19.10 Switching Characteristics - Serial Port ......................................................................................... 61
19.11 Switching Characteristics - Parallel Port (Multiplexed Mode) ...................................................... 62
19.12 Switching Characteristics- Parallel Port (Non-multiplexed Mode) ............................................... 65
19.13 Switching Characteristics - JTAG ................................................................................................. 68
COMPLIANT RECOMMENDATIONS AND SPECIFICATIONS ........................................................... 69
FBGA PACKAGE DIMENSIONS .......................................................................................................... 70
LQFP PACKAGE DIMENSIONS
..................................................................................................... 71
17.
18.
19.
20.
21.
22.
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LIST OF FIGURES
Figure 1. CS61884 144-Pin Outs ....................................................................................................... 7
Figure 2. CS61884 160-Ball FBGA Pin Outs .................................................................................... 8
Figure 3. G.703 BITS Clock Mode in NRZ Mode .......................................................................... 23
Figure 4. G.703 BITS Clock Mode in RZ Mode ............................................................................. 23
Figure 5. G.703 BITS Clock Mode in Remote Loopback ............................................................... 23
Figure 6. Pulse Mask at T1/J1 Interface .......................................................................................... 24
Figure 7. Pulse Mask at E1 Interface .............................................................................................. 24
Figure 8. Analog Loopback Block Diagram .................................................................................... 30
Figure 9. Analog Loopback with TAOS Block Diagram ................................................................ 30
Figure 10. Digital Loopback Block Diagram .................................................................................. 31
Figure 11. Digital Loopback with TAOS ........................................................................................ 31
Figure 12. Remote Loopback Block Diagram ................................................................................. 31
Figure 13. Serial Read/Write Format (SPOL = 0) ........................................................................... 33
Figure 14. Arbitrary Waveform UI .................................................................................................. 43
Figure 15. Test Access Port Architecture ........................................................................................ 45
Figure 16. TAP Controller State Diagram ....................................................................................... 46
Figure 17. Internal RX/TX Impedance Matching ............................................................................ 51
Figure 18. Internal TX, External RX Impedance Matching ............................................................ 52
Figure 19. Jitter Transfer Characteristic vs. G.736, TBR 12/13 & AT&T 62411 ........................... 58
Figure 20. Jitter Tolerance Characteristic vs. G.823 & AT&T 62411 ............................................ 58
Figure 21. Recovered Clock and Data Switching Characteristics ................................................... 60
Figure 22. Transmit Clock and Data Switching Characteristics ...................................................... 60
Figure 23. Signal Rise and Fall Characteristics ............................................................................... 60
Figure 24. Serial Port Read Timing Diagram .................................................................................. 61
Figure 25. Serial Port Write Timing Diagram ................................................................................. 61
Figure 26. Parallel Port Timing - Write; Intel Multiplexed Address / Data Bus Mode ................... 63
Figure 27. Parallel Mode Port Timing - Read; Intel Multiplexed Address / Data Bus Mode ........ 63
Figure 28. Parallel Port Timing - Write in Motorola Multiplexed Address / Data Bus .................. 64
Figure 29. Parallel Port Timing - Read in Motorola Multiplexed Address / Data Bus ................... 64
Figure 30. Parallel Port Timing - Write in Intel Non-Multiplexed Address / Data Bus Mode ....... 66
Figure 31. Parallel Port Timing - Read in Intel Non-Multiplexed Address / Data Bus Mode ........ 66
Figure 32. Parallel Port Timing - Write in Motorola Non-Multiplexed Address / Data Bus Mode 67
Figure 33. Parallel Port Timing - Read in Motorola Non-Multiplexed Address / Data Bus Mode . 67
Figure 34. JTAG Switching Characteristics .................................................................................... 68
DS485PP4
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Altera SoC
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