FAST CMOS
OCTAL D FLIP-FLOP
WITH MASTER RESET
Integrated Device Technology, Inc.
IDT54/74FCT273T/AT/CT
FEATURES:
•
•
•
•
Std., A, and C speed grades
Low input and output leakage
≤1µA
(max.)
CMOS power levels
True TTL input and output compatibility
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High drive outputs (-15mA I
OH
, 48mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
Available in DIP, SOIC, QSOP, CERPACK and LCC
packages
DESCRIPTION:
The IDT54/74FCT273T/AT/CT are octal D flip-flops built
using an advanced dual metal CMOS technology. The IDT54/
74FCT273T/AT/CT have eight edge-triggered D-type flip-
flops with individual D inputs and O outputs. The common
buffered Clock (CP) and Master Reset ( ) inputs load and
reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s O
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the
input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
MR
•
•
•
•
•
MR
FUNCTIONAL BLOCK DIAGRAM
D
0
CP
D
CP
R
D
MR
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
2568 drw 03
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
PIN CONFIGURATIONS
D
0
3
D
1
O
1
O
2
D
2
D
3
4
5
6
7
8
9 10 11 12 13
2568 drw 01
MR
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
2
3
4
5
6
7
8
9
10
19
P20-1
D20-1
SO20-2
SO20-8
&
E20-1
18
17
16
15
14
13
12
11
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
2
1
20 19
18
17
L20-2
16
15
14
D
7
D
6
O
6
O
5
D
5
O
0
1
20
V
CC
O
3
GND
CP
O
4
D
4
MR
V
CC
O
7
INDEX
2568 drw 02
DIP/SOIC/QSOP/CERPACK
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
LCC
TOP VIEW
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc.
APRIL 1995
DSC-4209/3
6.10
1
IDT54/74FCT273T/AT/CT FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names
D
N
MR
FUNCTION TABLE
(1)
Description
Operating Mode
Reset (Clear)
Load "1"
Load "0"
2568 tbl 01
MR
Data Inputs
Master Reset (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Outputs
Inputs
CP
X
↑
↑
D
N
X
h
I
Outputs
O
N
L
H
L
L
H
H
CP
O
N
NOTE:
2568 tbl 02
1. H = HIGH voltage level steady state
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock
transition
L = LOW voltage level steady state
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock
transition
X = Don’t Care
↑
= LOW-to-HIGH Clock Transition
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
V
TERM(2)
Terminal Voltage
–0.5 to +7.0
with Respect to
GND
V
TERM(3)
Terminal Voltage
–0.5 to
with Respect to
V
CC
+0.5
GND
T
A
Operating
0 to +70
Temperature
T
BIAS
Temperature
–55 to +125
Under Bias
T
STG
Storage
–55 to +125
Temperature
P
T
Power Dissipation
0.5
I
OUT
DC Output
Current
–60 to +120
Military
–0.5 to +7.0
Unit
V
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max. Unit
10
pF
12
pF
2568 lnk 04
–0.5 to
V
CC
+0.5
–55 to +125
–65 to +135
–65 to +150
0.5
–60 to +120
V
°C
°C
°C
W
mA
NOTE:
1. This parameter is measured at characterization but not tested.
2568 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
6.10
2
IDT54/74FCT273T/AT/CT FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
I H
I
I L
I
I
V
IK
I
OS
V
OH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= Min., I
N
= –18mA
V
CC
= Max.
(3)
, V
O
= GND
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –6mA MIL.
I
OH
= –8mA COM'L.
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L.
I
OL
= 32mA MIL.
I
OL
= 48mA COM'L.
—
Min.
2.0
—
—
—
—
—
–60
2.4
2.0
—
—
—
Typ.
(2)
—
—
—
—
—
–0.7
–120
3.3
3.0
0.3
200
0.01
Max.
—
0.8
±1
±1
±1
–1.2
–225
—
—
0.5
—
1
Unit
V
V
µA
µA
µA
V
mA
V
V
V
mV
mA
2568 tbl 05
V
I
= 2.7V
V
I
= 0.5V
V
CC
= Max., V
I
= V
CC
(Max.)
V
OL
V
H
I
CC
Output LOW Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= Max.
V
IN
=
GND or
V
CC
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test parameter for this parameter is
±5µA
at T
A
= -55°C.
6.10
3
IDT54/74FCT273T/AT/CT FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
MR
= V
CC
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
MR
=
V
CC
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
MR
=
V
CC
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle
Min.
—
V
IN
= V
CC
V
IN
= GND
—
Typ.
(2)
0.5
0.15
Max.
2.0
0.25
Unit
mA
mA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
—
1.5
3.5
mA
V
IN
= 3.4V
V
IN
= GND
—
2.0
5.5
V
IN
= V
CC
V
IN
= GND
—
3.8
7.3
5)
V
IN
= 3.4V
V
IN
= GND
—
6.0
16.3
(
5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
2568 tbl 06
6.10
4
IDT54/74FCT273T/AT/CT FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT273T
Com'l.
Symbol
Parameter
t
PLH
Propagation Delay
CP to O
N
t
PHL
t
PHL
t
SU
t
H
t
W
t
W
t
REM
Propagation Delay
MR
to O
N
Set-up Time HIGH or LOW
D
N
to CP
Hold Time HIGH or LOW D
N
to CP
CP Pulse Width HIGH or
LOW
MR
Pulse Width LOW
Recovery Time
MR
to CP
Condition
(1)
CL = 50pF
RL = 500Ω
IDT54/74FCT273AT
Com'l.
Mil.
IDT54/74FCT273CT
Com'l.
Mil.
Unit
ns
ns
ns
ns
ns
ns
ns
2568 tbl 07
Mil.
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max.
2.0 13.0
2.0 13.0
3.0
2.0
7.0
7.0
4.0
—
—
—
—
—
2.0 15.0
2.0 15.0
3.5
2.0
7.0
7.0
5.0
—
—
—
—
—
2.0
2.0
2.0
1.5
6.0
6.0
2.0
7.2
7.2
—
—
—
—
—
2.0
2.0
2.0
1.5
6.0
6.0
2.5
8.3
8.3
—
—
—
—
—
2.0
2.0
2.0
1.5
6.0
6.0
2.0
5.8
6.1
—
—
—
—
—
2.0
2.0
2.0
1.5
6.0
6.0
2.5
6.5
6.8
—
—
—
—
—
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
6.10
5
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