a
FEATURES
Single 3.0 V to 3.6 V Supply
14-Bit DAC Resolution and Input Data Width
160 MSPS Input Data Rate
67.5 MHz Reconstruction Passband @ 160 MSPS
74 dBc SFDR @ 25 MHz
2 Interpolation Filter with High- or Low-Pass Response
73 dB Image Rejection with 0.005 dB Passband Ripple
“Zero-Stuffing” Option for Enhanced Direct IF
Performance
Internal 2 /4 Clock Multiplier
250 mW Power Dissipation; 13 mW with Power-Down
Mode
48-Lead LQFP Package
APPLICATIONS
Communication Transmit Channel
W-CDMA Base Stations, Multicarrier Base Stations,
Direct IF Synthesis, Wideband Cable Systems
Instrumentation
PRODUCT DESCRIPTION
CLK+
CLK–
14-Bit, 160 MSPS TxDAC+
®
with 2 Interpolation Filter
AD9772A
FUNCTIONAL BLOCK DIAGRAM
CLKCOM CLKVDD MOD0 MOD1 RESET PLLLOCK DIV0 DIV1
AD9772A
CLOCK DISTRIBUTION
AND MODE SELECT
1
1 /2
FILTER
MUX
CONTROL CONTROL
PLL CLOCK
MULTIPLIER
2 /4
PLLCOM
LPF
PLLVDD
DATA
INPUTS
(DB13...
DB0)
SLEEP
EDGE-
TRIGGERED
LATCHES
2 FIR
INTER-
POLATION
FILTER
ZERO
STUFF
MUX
I
OUTA
14-BIT DAC
I
OUTB
REFIO
FSADJ
+1.2V REFERENCE
AND CONTROL AMP
DCOM DVDD
ACOM AVDD
REFLO
The AD9772A is a single-supply, oversampling, 14-bit digital-
to-analog converter (DAC) optimized for baseband or IF
waveform reconstruction applications requiring exceptional
dynamic range. Manufactured on an advanced CMOS process,
it integrates a complete, low distortion 14-bit DAC with a 2
digital interpolation filter and clock multiplier. The on-chip
PLL clock multiplier provides all the necessary clocks for the
digital filter and the 14-bit DAC. A flexible differential clock
input allows for a single-ended or differential clock driver for
optimum jitter performance.
For baseband applications, the 2 digital interpolation filter
provides a low-pass response, hence providing up to a threefold
reduction in the complexity of the analog reconstruction filter. It
does so by multiplying the input data rate by a factor of two
while simultaneously suppressing the original upper in-band
image by more than 73 dB. For direct IF applications, the 2
digital interpolation filter response can be reconfigured to select
the upper in-band image (i.e., high-pass response) while suppress-
ing the original baseband image. To increase the signal level of
the higher IF images and their passband flatness in direct IF
applications, the AD9772A also features a “zero stuffing” option
in which the data following the 2 interpolation filter is upsampled
by a factor of two by inserting midscale data samples.
The AD9772A can reconstruct full-scale waveforms with band-
widths as high as 67.5 MHz while operating at an input data rate of
160 MSPS. The 14-bit DAC provides differential current outputs
to support differential or single-ended applications. A segmented
TxDAC+ is a registered trademark of Analog Devices, Inc.
current source architecture is combined with a proprietary
switching technique to reduce spurious components and enhance
dynamic performance. Matching between the two current outputs
ensures enhanced dynamic performance in a differential output
configuration. The differential current outputs may be fed into a
transformer or a differential op amp topology to obtain a single-
ended output voltage using an appropriate resistive load.
The on-chip bandgap reference and control amplifier are config-
ured for maximum accuracy and flexibility. The AD9772A can
be driven by the on-chip reference or by a variety of external
reference voltages. The full-scale current of the AD9772A can
be adjusted over a 2 mA to 20 mA range, thus providing addi-
tional gain ranging capabilities.
The AD9772A is available in a 48-lead LQFP package and
specified for operation over the industrial temperature range
of –40°C to +85°C.
PRODUCT HIGHLIGHTS
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
1. A flexible, low power 2 interpolation filter supporting
reconstruction bandwidths of up to 67.5 MHz can be config-
ured for a low- or high-pass response with 73 dB of image
rejection for traditional baseband or direct IF applications.
2. A “zero-stuffing” option enhances direct IF applications.
3. A low glitch, fast settling 14-bit DAC provides exceptional
dynamic range for both baseband and direct IF waveform
reconstruction applications.
4. The AD9772A digital interface, consisting of edge-
triggered latches and a flexible differential or single-ended
clock input, can support input data rates up to 160 MSPS.
5. On-chip PLL clock multiplier generates all of the inter-
nal high-speed clocks required by the interpolation filter
and DAC.
6. The current output(s) of the AD9772A can easily be config-
ured for various single-ended or differential circuit topologies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD9772A–SPECIFICATIONS
DC SPECIFICATIONS
Parameter
RESOLUTION
DC ACCURACY
1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
Monotonicity (12-Bit)
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current
2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current
3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance (REFLO = 3 V)
Small Signal Bandwidth
TEMPERATURE COEFFICIENTS
Unipolar Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
POWER SUPPLY
AVDD
Voltage Range
Analog Supply Current (I
AVDD
)
Analog Supply Current in SLEEP Mode (I
AVDD
)
DVDD1, DVDD2
Voltage Range
Digital Supply Current (I
DVDD1
+ I
DVDD2
)
CLKVDD, PLLVDD
4
(PLLVDD = 3.0 V)
Voltage Range
Clock Supply Current (I
CLKVDD
+ I
PLLVDD
)
CLKVDD (PLLVDD = 0 V)
Voltage Range
Clock Supply Current (I
CLKVDD
)
Nominal Power Dissipation
5
Power Supply Rejection Ratio (PSRR)
6
– AVDD
Power Supply Rejection Ratio (PSRR)
6
– DVDD
OPERATING RANGE
NOTES
1
Measured at I
OUTA
driving a virtual ground.
2
Nominal full-scale current, I
OUTFS
, is 32 the I
REF
current.
3
Use an external amplifier to drive any external load.
4
Measured at f
DATA
= 100 MSPS and f
OUT
= 1 MHz, DIV1, DIV0 = 0 V.
5
Measured with PLL enabled at f
DATA
= 50 MSPS and f
OUT
= 1 MHz.
6
Measured over a 3.0 V to 3.6 V range.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I
OUTFS
= 20 mA, unless otherwise noted.)
Min
14
±
3.5
±
2.0
Guaranteed Over Specified Temperature Range
–0.025
–2
–5
–1.0
200
3
1.14
1.20
1
1.26
+0.025
+2
+5
+1.25
Typ
Max
Unit
Bits
LSB
LSB
±
0.5
±
1.5
20
% of FSR
% of FSR
% of FSR
mA
V
kΩ
pF
V
µA
V
mΩ
MHz
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
0.1
10
0.5
0
±
50
±
100
±
50
1.25
3.1
3.3
34
4.3
3.3
37
3.3
25
3.3
6.0
253
3.5
37
6
3.5
40
3.5
30
3.5
272
+0.6
+0.025
+85
V
mA
mA
V
mA
V
mA
V
mA
mW
% of FSR/V
% of FSR/V
°C
3.1
3.1
3.1
–0.6
–0.025
–40
–2–
REV. A
AD9772A
DYNAMIC SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
Maximum DAC Output Update Rate (f
DAC
)
Output Settling Time (t
ST
) (to 0.025%)
Output Propagation Delay
1
(t
PD
)
Output Rise Time (10% to 90%)
2
Output Fall Time (10% to 90%)
2
Output Noise (I
OUTFS
= 20 mA)
AC LINEARITY—BASEBAND MODE
Spurious-Free Dynamic Range (SFDR) to Nyquist (f
OUT
= 0 dBFS)
f
DATA
= 65 MSPS; f
OUT
= 1.01 MHz
f
DATA
= 65 MSPS; f
OUT
= 10.01 MHz
f
DATA
= 65 MSPS; f
OUT
= 25.01 MHz
f
DATA
= 160 MSPS; f
OUT
= 5.02 MHz
f
DATA
= 160 MSPS; f
OUT
= 20.02 MHz
f
DATA
= 160 MSPS; f
OUT
= 50.02 MHz
Two-Tone Intermodulation (IMD) to Nyquist (f
OUT1
= f
OUT2
= –6 dBFS)
f
DATA
= 65 MSPS; f
OUT1
= 5.01 MHz; f
OUT2
= 6.01 MHz
f
DATA
= 65 MSPS; f
OUT1
= 15.01 MHz; f
OUT2
= 17.51 MHz
f
DATA
= 65 MSPS; f
OUT1
= 24.1 MHz; f
OUT2
= 26.2 MHz
f
DATA
= 160 MSPS; f
OUT1
= 10.02 MHz; f
OUT2
= 12.02 MHz
f
DATA
= 160 MSPS; f
OUT1
= 30.02 MHz; f
OUT2
= 35.02 MHz
f
DATA
= 160 MSPS; f
OUT1
= 48.2 MHz; f
OUT2
= 52.4 MHz
Total Harmonic Distortion (THD)
f
DATA
= 65 MSPS; f
OUT
= 1.0 MHz; 0 dBFS
f
DATA
= 78 MSPS; f
OUT
= 10.01 MHz; 0 dBFS
Signal-to-Noise Ratio (SNR)
f
DATA
= 65 MSPS; f
OUT
= 16.26 MHz; 0 dBFS
f
DATA
= 100 MSPS; f
OUT
= 25.1 MHz; 0 dBFS
Adjacent Channel Power Ratio (ACPR)
WCDMA with 4.1 MHz BW, 5 MHz Channel Spacing
IF = 16 MHz, f
DATA
= 65.536 MSPS
IF = 32 MHz, f
DATA
= 131.072 MSPS
Four-Tone Intermodulation
15.6 MHz, 15.8 MHz, 16.2 MHz and 16.4 MHz at –12 dBFS
f
DATA
= 65 MSPS, Missing Center
AC LINEARITY—IF MODE
Four-Tone Intermodulation at IF = 70 MHz
68.1 MHz, 69.3 MHz, 71.2 MHz and 72.0 MHz at –20 dBFS
f
DATA
= 52 MSPS, f
DAC
= 208 MHz
NOTES
1
Propagation delay is delay from CLK input to DAC update.
2
Measured single-ended into 50
Ω
load.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I
OUTFS
= 20 mA,
differential transformer coupled output, 50 doubly terminated, unless otherwise noted.)
Min
400
11
17
0.8
0.8
50
Typ
Max
Unit
MSPS
ns
ns
ns
ns
pA√Hz
82
75
73
82
75
65
85
75
68
85
70
65
–80
–74
71
71
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
dB
dB
dB
78
68
88
dBc
dBc
dBFS
77
dBFS
REV. A
–3–
AD9772A
DIGITAL FILTER SPECIFICATIONS
Parameter
MAXIMUM INPUT DATA RATE (f
DATA
)
DIGITAL FILTER CHARACTERISTICS
Passband Width
1
: 0.005 dB
Passband Width: 0.01 dB
Passband Width: 0.1 dB
Passband Width: –3 dB
LINEAR PHASE (FIR IMPLEMENTATION)
STOPBAND REJECTION
0.606 f
CLOCK
to 1.394 f
CLOCK
GROUP DELAY
2
IMPULSE RESPONSE DURATION
–40 dB
–60 dB
NOTES
1
Excludes sin(x)/x characteristic of DAC.
2
Defined as the number of data clock cycles between impulse input and peak of output response.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I
OUTFS
= 20 mA,
differential transformer coupled output, 50 doubly terminated, unless otherwise noted.)
Min
150
0.401
0.404
0.422
0.479
Typ
Max
Unit
MSPS
f
OUT
/f
DATA
f
OUT
/f
DATA
f
OUT
/f
DATA
f
OUT
/f
DATA
73
21
36
42
dB
Input Clocks
Input Clocks
Input Clocks
0
Table I. Integer Filter Coefficients for Interpolation Filter
(43-Tap Half-Band FIR Filter)
–20
–40
OUTPUT – dB
Lower
Coefficient
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(7)
H(8)
H(9)
H(10)
H(11)
H(12)
H(13)
H(14)
H(15)
H(16)
H(17)
H(18)
H(19)
H(20)
H(21)
H(22)
Upper
Coefficient
H(43)
H(42)
H(41)
H(40)
H(39)
H(38)
H(37)
H(36)
H(35)
H(34)
H(33)
H(32)
H(31)
H(30)
H(29)
H(28)
H(27)
H(26)
H(25)
H(24)
H(23)
Integer
Value
10
0
–31
0
69
0
–138
0
248
0
–419
0
678
0
–1083
0
1776
0
–3282
0
10364
16384
–60
–80
–100
–120
–140
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
FREQUENCY – DC TO
f
DATA
0.8
0.9
1
Figure 2a. FIR Filter Frequency Response—Baseband Mode
1
0.8
NORMALIZED OUTPUT
0.6
0.4
0.2
0
–0.2
–0.4
0
5
10
15
20
25
30
TIME – Samples
35
40
45
Figure 2b. FIR Filter Impulse Response—Baseband Mode
REV. A
–5–
Microcontroller MCU
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