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DS635 (v2.0) September 9, 2009
Product Specification
www.xilinx.com
1
R
Key Feature Differences from Commercial XC Devices
•
AEC-Q100 device qualification and full production part
approval process (PPAP) documentation support
available in both extended temperature I- and
Q-Grades
Guaranteed to meet full electrical specification over the
T
J
= –40°C to +125°C temperature range (Q-Grade)
XA Spartan-3E devices are available in the -4 speed
grade only.
PCI-66 is not supported in the XA Spartan-3E FPGA
product line.
The readback feature is not supported in the XA
•
•
•
•
•
•
Spartan-3E FPGA product line.
XA Spartan-3E devices are available in Step 1 only.
JTAG configuration frequency reduced from 30 MHz to
25 MHz.
Platform Flash is not supported within the XA family.
XA Spartan-3E devices are available in Pb-free
packaging only.
MultiBoot is not supported in XA versions of this
product.
The XA Spartan-3E device must be power cycled prior
to reconfiguration.
•
•
•
•
Table 1:
Summary of XA Spartan-3E FPGA Attributes
Equivalent
Logic
Rows Columns
Cells
2,160
5,508
10,476
19,512
33,192
22
34
46
60
76
16
26
34
46
58
CLB Array
(One CLB = Four Slices)
Total
CLBs
240
612
1,164
2,168
3,688
Total
Slices
960
2,448
4,656
8,672
14,752
Distributed
RAM bits
(1)
15K
38K
73K
136K
231K
Block
RAM
bits
(1)
72K
216K
360K
504K
648K
Maximum
Maximum Differential
I/O Pairs
User I/O
108
172
190
304
376
40
68
77
124
156
Device
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
System
Gates
100K
250K
500K
1200K
1600K
Dedicated
Multipliers DCMs
4
12
20
28
36
2
4
4
8
8
Notes:
1.
By convention, one Kb is equivalent to 1,024 bits.
Architectural Overview
The XA Spartan-3E family architecture consists of five fun-
damental programmable functional elements:
•
Configurable Logic Blocks (CLBs)
contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
Input/Output Blocks (IOBs)
control the flow of data
between the I/O pins and the internal logic of the
device. Each IOB supports bidirectional data flow plus
3-state operation. Supports a variety of signal
standards, including four high-performance differential
standards. Double Data-Rate (DDR) registers are
included.
Block RAM
provides data storage in the form of
18-Kbit dual-port blocks.
Multiplier Blocks
accept two 18-bit binary numbers as
inputs and calculate the product.
•
Digital Clock Manager (DCM) Blocks
provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
•
These elements are organized as shown in
Figure 1.
A ring
of IOBs surrounds a regular array of CLBs. Each device has
two columns of block RAM except for the XA3S100E, which
has one column. Each RAM column consists of several
18-Kbit RAM blocks. Each block RAM is associated with a
dedicated multiplier. The DCMs are positioned in the center
with two at the top and two at the bottom of the device. The
XA3S100E has only one DCM at the top and bottom, while
the XA3S1200E and XA3S1600E add two DCMs in the mid-
dle of the left and right sides.
The XA Spartan-3E family features a rich network of traces
that interconnect all five functional elements, transmitting
signals among them. Each functional element has an asso-
ciated switch matrix that permits multiple connections to the
routing.
•
•
DS635 (v2.0) September 9, 2009
Product Specification
www.xilinx.com
2
R
Notes:
1.
The XA3S1200E and XA3S1600E have two additional DCMs on both the left and right sides as
indicated by the dashed lines. The XA3S100E has only one DCM at the top and one at the bottom.
Figure 1:
XA Spartan-3E Family Architecture
Configuration
XA Spartan-3E FPGAs are programmed by loading config-
uration data into robust, reprogrammable, static CMOS con-
figuration latches (CCLs) that collectively control all
functional elements and routing resources. The FPGA’s
configuration data is stored externally in a PROM or some
other non-volatile medium, either on or off the board. After
applying power, the configuration data is written to the
FPGA using any of five different modes:
•
•
•
•
•
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
Byte Peripheral Interface (BPI) Up or Down from an
industry-standard x8 or x8/x16 parallel NOR Flash
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
Boundary Scan (JTAG), typically downloaded from a
processor or system tester.
I/O Capabilities
The XA Spartan-3E FPGA SelectIO interface supports
many popular single-ended and differential standards.
Table 2
shows the number of user I/Os as well as the num-
ber of differential I/O pairs available for each device/pack-
age combination.
XA Spartan-3E FPGAs support the following single-ended
standards:
•
•
•
•
•
3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
3V PCI at 33 MHz
HSTL I and III at 1.8V, commonly used in memory
applications
SSTL I at 1.8V and 2.5V, commonly used for memory
applications
DS635 (v2.0) September 9, 2009
Product Specification
www.xilinx.com
3
R
XA Spartan-3E FPGAs support the following differential
standards:
•
•
•
•
LVDS
Bus LVDS
mini-LVDS
RSDS
•
•
•
Differential HSTL (1.8V, Types I and III)
Differential SSTL (2.5V and 1.8V, Type I)
2.5V LVPECL inputs
Table 2:
Available User I/Os and Differential (Diff) I/O Pairs
Package
Size (mm)
Device
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
Notes:
1.
2.
All XA Spartan-3E devices provided in the same package are pin-compatible as further described in Module 4: Pinout Descriptions of
DS312.
The number shown in
bold
indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins.
VQG100
16 x 16
User
66
(7)
66
(7)
-
-
-
Diff
30
(2)
30
(2)
-
-
-
CPG132
8x8
User
83
(11)
92
(7)
92
(7)
-
-
Diff
35
(2)
41
(2)
41
(2)
-
-
TQG144
22 x 22
User
108
(28)
108
(28)
-
-
-
Diff
40
(4)
40
(4)
-
-
-
PQG208
28 x 28
User
-
158
(32)
158
(32)
-
-
Diff
-
65
(5)
65
(5)
-
-
FTG256
17 x 17
User
-
172
(40)
190
(41)
190
(40)
-
Diff
-
68
(8)
77
(8)
77
(8)
-
FGG400
21 x 21
User
-
-
-
304
(72)
304
(72)
Diff
-
-
-
124
(20)
124
(20)
FGG484
23 x 23
User
-
-
-
-
376
(82)
Diff
-
-
-
-
156
(21)
DS635 (v2.0) September 9, 2009
Product Specification
www.xilinx.com
4
R
Package Marking
Figure 2
provides a top marking example for XA Spartan-3E
FPGAs in the quad-flat packages.
Figure 3
shows the top
marking for XA Spartan-3E FPGAs in BGA packages
except the 132-ball chip-scale package (CPG132). The
markings for the BGA packages are nearly identical to those
for the quad-flat packages, except that the marking is
rotated with respect to the ball A1 indicator.
Figure 4
shows
the top marking for XA Spartan-3E FPGAs in the CPG132
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