8-BIT PROGRAMMABLE DELAY LINE
Parameter Name | Attribute value |
Is it lead-free? | Lead free |
Is it Rohs certified? | conform to |
Maker | Data Delay Devices |
Parts packaging code | DIP |
package instruction | DIP, |
Contacts | 40 |
Reach Compliance Code | compli |
JESD-30 code | R-XDIP-T40 |
JESD-609 code | e3 |
Logic integrated circuit type | ACTIVE DELAY LINE |
Number of functions | 1 |
Number of taps/steps | 255 |
Number of terminals | 40 |
Output polarity | COMPLEMENTARY |
Package body material | UNSPECIFIED |
encapsulated code | DIP |
Package shape | RECTANGULAR |
Package form | IN-LINE |
Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
programmable delay line | YES |
Certification status | Not Qualified |
Maximum seat height | 7.493 mm |
Maximum supply voltage (Vsup) | 5.25 V |
Minimum supply voltage (Vsup) | 4.75 V |
Nominal supply voltage (Vsup) | 5 V |
surface mount | NO |
Terminal surface | Tin (Sn) |
Terminal form | THROUGH-HOLE |
Terminal pitch | 2.54 mm |
Terminal location | DUAL |
Maximum time at peak reflow temperature | NOT SPECIFIED |
Total delay nominal (td) | 1020 ns |
width | 15.24 mm |