ASTMLPFL-28-77.760MHZ-EC-S-T3 datasheet, PDF

ASTMLPFL-28-77.760MHZ-EC-S-T3: DescriptionLVCMOS Output Clock Oscillator, 77.76MHz Nom, SMD, 4 PIN; CategoryPassive components oscillator; File Size3MB，13 Pages; ManufacturerAbracon; Websitehttp://www.abracon.com/index.htm; Environmental Compliance

Download Datasheet Parametric View All

ASTMLPFL-28-77.760MHZ-EC-S-T3 Overview

LVCMOS Output Clock Oscillator, 77.76MHz Nom, SMD, 4 PIN

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	7283579515
package instruction	SMD, 4 PIN
Reach Compliance Code	compliant
Other features	STANDBY; ENABLE/DISABLE FUNCTION; TR, 13 INCH
maximum descent time	2 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
Installation features	SURFACE MOUNT
Number of terminals	4
Nominal operating frequency	77.76 MHz
Maximum operating temperature	70 °C
Minimum operating temperature	-20 °C
Oscillator type	LVCMOS
Output load	15 pF
physical size	5.0mm x 3.2mm x 0.75mm
longest rise time	2 ns
Maximum supply voltage	3.08 V
Minimum supply voltage	2.52 V
Nominal supply voltage	2.8 V
surface mount	YES
maximum symmetry	55/45 %

Smart Home Energy Management with Levarys and Qorvo Technologies: Low-power Qorvo chips enhance connectivity and reliability for new Luna smart home systemImagine a smart home system with modern thermostats, smart radiator valves, temperature/door/window sensors and...; 石榴姐 RF/Wirelessly

Analog Circuit Practical Knowledge Lectures (12 lectures) in Chinese for free: Browser download: http://cajviewer.cnki.net/cajview_page/CAJViewer5.5.exe Related keywords:Analog circuitlectureChineseknowledge...; fighting Analog electronics

Use FPGA to simulate USB function (written in VHDL language).rar: Use FPGA to simulate USB function (written in VHDL language).rar...; zxopenljx EE_FPGA Learning Park

The internal crystal oscillator of SMIC 5897 is inaccurate: Taking the baud rate of 115200 as an example, the code is written as eight-bit asynchronous. When the serial port debugging assistant communicates, the baud rate is set to 115200 and the stop bit is 1...; 一眼呆 51mcu

KEYENCE Fiber Optic Sensor Disassembly: [i=s]This post was last edited by littleshrimp on 2022-10-23 09:34[/i]What we are going to disassemble this time is a set of Keyence fiber optic sensor combination, which includes a FS-V1 with a scree...; littleshrimp Sensor

FPGA Simplified Design Method Case 4 [12401003385]: [b][font=宋体]Classic cases of minimalist design method[/font]4[/b][align=left] [/align][align=left][font=宋体]Case[/font]4.When receiving en=1, dout generates a high level pulse of 2 clock cycles after 1...; guyu_1 FPGA/CPLD

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components