3Q0
FS
VCCQ
REF
GND
TEST
2F1
VCCN
FB
VCCN
2Q1
2Q0
3Q1
3Q0
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver
SuperClock
®
Description
Features
PI6C3Q99X family provides following products:
PI6C3Q991: 32-pin PLCC version
PI6C3Q993: 28-pin QSOP version
Inputs are 5V I/O Tolerant
4 pairs of programmable skew outputs
Low skew: 200ps same pair; 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Output frequency: 3.75 MHz to 85 MHz
2x, 4x, 1/2, and 1/4 outputs
3 skew grades:
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: < 200ps peak-to-peak
Industrial temperature range
Pin-to-pin compatible with IDT QS5V991 and QS5V993
Available in 32-pin PLCC and 28-pin QSOP
The PI6C3Q99X family is a high fanout 3.3V PLL-based clock driver
intended for high performance computing and data-communica-
tions applications. A key feature of the programmable skew is the
ability of outputs to lead or lag the REF input signal. The PI6C3Q991
has 8 programmable skew outputs in 4 banks of 2, while the
PI6C3Q993 has 6 programmable skew outputs and 2 zero skew
outputs. Skew is controlled by 3-level input signals that may be hard-
wired to appropriate HIGH-MID-LOW levels.
When the GND/sOE pin is held low, all the outputs are synchro-
nously enabled. However, if GND/sOE is held high, all the outputs
except 3Q0 and 3Q1 are synchronously disabled. Furthermore, when
the V
CCQ
/PE is held high, all the outputs are synchronized with the
positive edge of the REF clock input. When V
CCQ
/PE is held low,
all the outputs are synchronized with the negative edge of REF. Both
devices have LVTTL outputs with 12mA balanced drive outputs.
Pin Configurations
PI6C3Q991
REF
VCCQ
FS
PI6C3Q993
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
GND
TEST
2F1
2F0
GND/sOE
1F1
1F0
VCCN
1Q0
1Q1
GND
GND
2Q0
2Q1
3F1
4F0
4F1
VCCQ/PE
VCCN
4Q1
4Q0
GND
GND
4
5
6
7
8
9
10
11
12
13
14
1 32 31 30
29
28
27
26
32-Pin
25
J
24
23
22
21
15 16 17 18 19 20
3 2
2F0
GND/sOE
1F1
1F0
VCCN
1Q0
1Q1
GND
GND
3F0
3F1
VCCQ/PE
VCCN
4Q1
4Q0
GND
3Q1
3Q0
VCCN
FB
28-Pin
Q
23
22
21
20
19
18
17
16
15
1
PS8449A
10/09/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C3Q991, PI6CQ3993
3.3V Programmable Skew PLL Clock Driver
SuperClock
®
Logic Block Diagrams
PI6C3Q991
GND/sOE
Skew
Select
3
V
CCQ
/PE
Skew
Select
REF
FB
3
FS
Skew
Select
3
3
4F1:0
3
PLL
Skew
Select
3
3
3F1:0
4Q0
4Q1
3
2F1:0
3Q0
3Q1
3
1F1:0
2Q0
2Q1
REF
FB
3
FS
PLL
Skew
Select
3
3
3F1:0
4Q0
4Q1
PI6C3Q993
GND/sOE
1Q0
1Q1
V
CCQ
/PE
Skew
Select
3
3
1F1:0
Skew
Select
3
3
2F1:0
1Q0
1Q1
2Q0
2Q1
3Q0
3Q1
Pin Descriptions
Pin Name
REF
FB
TEST
(1)
Type
IN
IN
IN
Reference Clock input
Feedback Input
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections
(see table 3) remain in effect. Set LO W for normal operation.
Synchronous O utput Enable. When HIGH, it stops clock outputs (except 3Q 0 and 3Q 1) in a LO W state - 3Q 0
or 3Q 1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and
GND/sO E is HIGH, the nF [1:0] pins act as output disable controls for individual banks when nF [1:0] = LL.
Set GND/sO E LO W for normal operation.
Selectable positive or negative edge control. When LO W/HIGH the outputs are synchronized with the
negative/positive edge of the reference clock.
3- level inputs for selecting 1 of 9 skew taps or frequency range.
Selects appropriate oscillator circuit based on anticipated frequency range. See table 2
4 output banks of 2 outputs, with programmable skew. O n the PI6C3Q 993 4Q 1:0 are fixed zero skew outputs.
Power supply for output buffers
Power supply for phase locked loop and other internal circuitry
Ground
Functional D e s cription
GND/sO E
(1)
IN
V
CCQ
/PE
nF [1:0]
FS
nQ [1:0]
V
CCN
V
CCQ
GND
IN
IN
IN
O UT
PWR
PWR
PWR
Note:
1. When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[1:0] =LL functioning as an output disable control for
individual output banks. Skew selections (see Table 3) remain in effect unless nF[1:0] = LL.
2
PS8449A
10/09/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver
SuperClock
®
External Feedback
By providing external feedback, the PI6C3Q99X family gives users
flexibility with regard to skew adjustment. The FB signal is compared
with the input REF signal at the phase detector in order to drive the
VCO. Phase differences cause the VCO of the PLL to adjust upwards
or downwards accordingly. An internal loop filter moderates the
response of the VCO to the phase detector. The loop filter transfer
function has been chosen to provide minimal jitter (or frequency
variation) while still providing accurate responses to input fre-
quency changes.
Programmable Skew
Output skew with respect to the REF input is adjustable to compen-
sate for PCB trace delays, backplane propagation delays or to
accommodate requirements for special timing relationships between
clocked components. Skew is selectable as a multiple of a time unit
t
U
which is of the order of a nanosecond (see Table 2). There are 9
skew configurations available for each output pair. These configu-
rations are choosen by the nF1:0 control pins. In order to minimize
the number of control pins, 3-level inputs (HIGH-MID-LOW) are
used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew
is not a requirement, the control pins can be left open for the zero skew
default setting. The Skew Selection Table (Table 3) shows how to
select specific skew taps by using the nF1:0 control pins.
Table 2. PLL Programmable Skew Range and Resolution Table
FS = LOW
Timing unit calculation (t
U
)
VCO frequency range (F
NOM
)
(1,2)
Skew adjustment range
(3)
Max.
adjustment
Example 1, F
NOM
= 15 MHz
Example 2, F
NOM
= 25 MHz
Example 3, F
NOM
= 30 MHz
Example 4, F
NOM
= 40 MHz
Example 5, F
NOM
= 50 MHz
Example 6, F
NOM
= 80 MHz
1/(44xF
NOM
)
15 to 35 MHz
±9.09ns
±49°
±14%
t
U
= 1.52ns
t
U
= 0.91ns
t
U
= 0.76ns
t
U
= 1.54ns
t
U
= 1.28ns
t
U
= 0.96ns
t
U
= 0.77ns
t
U
= 1.56ns
t
U
= 1.25ns
t
U
= 0.78ns
FS = M ID
1/(26xF
NOM
)
±9.23ns
±83°
±23%
FS = HIGH
1/(16xF
NOM
)
±9.38ns
±135°
±37%
Comme nts
25 to 60 MHz 40 to 85 MHz
ns Phase degrees
% of cycle time
Notes:
1. The device may be operated outside recommended frequency ranges without damage, but functional
operation is not guaranteed. Selecting the appropriate FS value based on input frequency range allows the
PLL to operate in its sweet spot where jitter is lowest.
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator.
The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their
undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the
output connected to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO
frequency when the part is configured for a frequency multiplication by using a divided output as the FB input.
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used
for feedback, then adjustment range will be greater. For example if a 4t
U
skewed output is used for feedback,
all other outputs will be skewed 4t
U
in addition to whatever skew value is programmed for those outputs.
Max adjustment range applies to output pairs 3 and 4 where ±6 t
U
skew adjustment is possible and at the
lowest F
NOM
value.
3
PS8449A
10/09/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C3Q991, PI6CQ3993
3.3V Programmable Skew PLL Clock Driver
SuperClock
®
Table 3. Skew Selection Table for Output Pairs
nF1:0
LL
(2)
LM
LH
ML
MM
MH
HL
HM
HH
Ske w (Pair #1, #2)
4t
U
3t
U
2t
U
1t
U
Zero skew
+1t
U
+2t
U
+3t
U
+4t
U
Ske w (Pair #3)
Divide by 2
6t
U
4t
U
2t
U
Zero skew
+2t
U
+4t
U
+6t
U
Divide by 4
Ske w (Pair #4)
(1)
Divide by 2
6t
U
4t
U
2t
U
Zero skew
+2t
U
+4t
U
+6t
U
Inverted
(3)
Notes:
1. Programmable skew on pair #4 is not applicable
for the PI6C993.
2. LL disables outputs if TEST = MID and GND/
sOE = HIGH.
3. When pair #4 is set to HH (inverted), GND/sOE
disables pair #4 HIGH when V
CCQ
/PE = HIGH,
GND/sOE disables pair #4 LOW when V
CCQ
/
PE = LOW
Table 4. Absolute Maximum Ratings
Supply Voltage to ground ........................................................ 0.5V to 7.0V
DC input Voltage V
I ....................................................................
0.5V to V
CC
+ 0.5V
Maximum Power Dissipation at T
A
= 85°C, PLCC ......................... 0.80 watts
QSOP ....................... 0.66 watts
TSTG Storage temperature ....................................................65°C to 150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the
device at these or any other conditions above those listed in
the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Table 5. Recommended Operating Range
Symbol
D e s cription
PI6C3Q99X
PI6C3Q99X-5
(Indus trial)
M in.
V
CC
T
A
Power Supply
Voltage
Ambient O perating
Temperature
3.0
40
M ax.
3.6
85
PI6C399X-2
(Comme rcial)
M in.
3.0
0
M ax.
3.6
70
V
°C
Units
4
PS8449A
10/09/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver
SuperClock
®
Table 6. DC Characteristics Over Operating Range
Symbol
V
IH
V
IL
V
IHH
V
IMM
V
ILL
I
IN
I
3
I
PU
I
PD
V
OH
V
OL
Parame te r
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
(1)
Te s t Condition
Guaranteed Logic HIGH
(REF, FB inputs only)
Guaranteed Logic LOW
(REF, FB inputs only)
3- Level Inputs Only
3- Level Inputs Only
3- Level Inputs Only
V
IN
= V
CC
or GND,
V
CC
= Max.
V
IN
= V
CC
V
IN
= V
CC
/2
V
IN
= GND
HIGH Level
MID Level
LOW Level
M in.
2.0
M ax.
Units
0.8
V
CC
0.6
V
CC
/2 0.3
V
CC
/2 +0.3
0.6
5
200
50
200
100
100
2.2
0.55
V
V
Input MID Voltage
(1)
Input LOW Voltage
(1)
Input Leakage Current (REF,
FB inputs only)
3- Level Input DC Current
(TEST, FS, nF1:0)
Input Pull- Up Current
(V
CCQ
/PE)
Input Pull- Down Current
(GND/sOE)
Output HIGH Voltage
Output LOW Voltage
µA
V
CC
= Max., V
IN
= GND
V
CC
= Max., V
IN
= V
CC
V
CC
= Min., I
OH =
12mA
V
CC
= Min., I
OL =
12mA
Note:
1. These inputs are normally wired to V
CC
, GND, or unconnected. Internal termination resistors bias unconnected inputs
to V
CC
/2. If these inputs are switched, the function and timing of the outputs may glitched, and the PLL may require
an additional t
LOCK
time before all datasheet limits are achieved.
Table 7. Power Supply Characteristics
Symbol
I
CCQ
∆I
CC
I
CCD
I
C
I
C
I
C
Parame te r
Quiescent Power Supply Current
Power Supply Current per Input HIGH
(1)
Total Power Supply Current
(1)
Total Power Supply Current
(1)
Total Power Supply Current
(1)
Te s t Condition
V
CC
= Max., TEST = Mid., REF = LOW,
GND/sO E = LOW, All outputs unloaded
V
CC
= Max., V
IN
= 3.0V
V
CC
= 3.3V, F
REF
= 20 MHz, C
L
= 160pF
(2)
V
CC
= 3.3V, F
REF
= 33 MHz, C
L
= 160pF
(2)
V
CC
= 3.3V, F
REF
= 66 MHz, C
L
= 160pF
(2)
Typ.
8.0
1.0
55
29
42
76
mA
M ax.
15
30
90
Units
mA
µA
µA/MHz
Dynamic Power Supply Current per Output
(1)
V
CC
= Max., C
L
= 0pF
Notes:
1. Guaranteed by characterization but not production tested.
2. For 8 outputs each loaded with 20pF.
5
PS8449A
10/09/00
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