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PIC17CR42T-25I/P

Description
8-BIT, OTPROM, 33 MHz, RISC MICROCONTROLLER, PQCC44
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size59KB,4 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Environmental Compliance
Download Datasheet Parametric View All

PIC17CR42T-25I/P Overview

8-BIT, OTPROM, 33 MHz, RISC MICROCONTROLLER, PQCC44

PIC17CR42T-25I/P Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerMicrochip
Parts packaging codeDIP
package instruction0.600 INCH, PLASTIC, DIP-40
Contacts40
Reach Compliance Codecompli
Has ADCNO
Address bus width16
bit size8
maximum clock frequency25 MHz
DAC channelNO
DMA channelNO
External data bus width16
JESD-30 codeR-PDIP-T40
JESD-609 codee3
length51.26 mm
Number of I/O lines33
Number of terminals40
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
PWM channelYES
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
ROM programmabilityMROM
Maximum seat height4.06 mm
speed25 MHz
Maximum supply voltage6 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width15.24 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER, RISC
PIC17C44
PIC17C44 Rev. A Silicon Errata Sheet
The PIC17C44 (Rev. A) parts you have received con-
form functionally to the PIC17C4X preliminary data
sheet (DS30412
C
), except for the following clarifica-
tions and corrections.
NONE
Clarifications/Corrections to the Data Sheet:
The PIC17C44 Preliminary Data Sheet (document
DS30412
C
) that you have received, requires the follow-
ing clarifications and corrections.
1.
The clearing of any interrupt enable bit(s) in the
INTSTA register should be preceded by the dis-
abling of the global interrupt control bit (setting
GLINTD). Global interrupts may then be re-
enabled. The individual interrupts may be re-
enabled without further control of the GLINTD
bit.
When global interrupts are enabled, if the interrupt
flag is being set when the corresponding enable bit
is being cleared the device will branch to the reset
vector address (0h). The interrupt flag will not be
(automatically) cleared.
2.
The
RETURN
instruction causes an update of the
PCLATH register. The PCLATH register is
loaded with the high address of the
RETURN
instruction.
The Table write to internal program memory (self
programming) can occur even when the MCLR
pin is either at the V
IH
or V
IHH
voltage level.
When the MCLR pin is at V
IH
, the table write
sequence occurs, but the programming voltage
is marginal since the MCLR pin is not at the cor-
rect level. This table write may cause the speci-
fied program memory location to be corrupted
(depending on the data in the TABLAT register).
3.
Note:
As with any windowed EPROM device, please cover the window at all times, except when erasing.
©
October, 1997 Microchip Technology Inc.
DS30412C/44/E1A2-page 1

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