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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
AM1808 ARM
®
Microprocessor
1 AM1808 ARM Microprocessor
1.1
1
Features
• Programmable Real-Time Unit Subsystem
(PRUSS)
– Two Independent Programmable Real-Time Unit
(PRU) Cores
• 32-Bit Load-Store RISC Architecture
• 4KB of Instruction RAM per Core
• 512 Bytes of Data RAM per Core
• PRUSS can be Disabled via Software to
Save Power
• Register 30 of Each PRU is Exported from
the Subsystem in Addition to the Normal R31
Output of the PRU Cores.
– Standard Power-Management Mechanism
• Clock Gating
• Entire Subsystem Under a Single PSC Clock
Gating Domain
– Dedicated Interrupt Controller
– Dedicated Switched Central Resource
• USB 1.1 OHCI (Host) with Integrated PHY (USB1)
• USB 2.0 OTG Port with Integrated PHY (USB0)
– USB 2.0 High- and Full-Speed Client
– USB 2.0 High-, Full-, and Low-Speed Host
– End Point 0 (Control)
– End Points 1,2,3,4 (Control, Bulk, Interrupt or
ISOC) RX and TX
• One Multichannel Audio Serial Port (McASP):
– Transmit and Receive Clocks
– Two Clock Zones and 16 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– DIT-Capable
– FIFO Buffers for Transmit and Receive
• Two Multichannel Buffered Serial Ports (McBSPs):
– Transmit and Receive Clocks
– Supports TDM, I2S, and Similar Formats
– AC97 Audio Codec Interface
– Telecom Interfaces (ST-Bus, H100)
– 128-Channel TDM
– FIFO Buffers for Transmit and Receive
• 10/100 Mbps Ethernet MAC (EMAC):
– IEEE 802.3 Compliant
– MII Media-Independent Interface
– RMII Reduced Media-Independent Interface
– Management Data I/O (MDIO) Module
• 375- and 456-MHz ARM926EJ-S™ RISC MPU
• ARM926EJ-S Core
– 32-Bit and 16-Bit ( Thumb
®
) Instructions
– Single-Cycle MAC
– ARM Jazelle
®
Technology
– Embedded ICE-RT™ for Real-Time Debug
• ARM9™ Memory Architecture
– 16KB of Instruction Cache
– 16KB of Data Cache
– 8KB of RAM (Vector Table)
– 64KB of ROM
• Enhanced Direct Memory Access Controller 3
(EDMA3):
– 2 Channel Controllers
– 3 Transfer Controllers
– 64 Independent DMA Channels
– 16 Quick DMA Channels
– Programmable Transfer Burst Size
• 128KB of On-Chip Memory
• 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and
DDR2 Interfaces)
• Two External Memory Interfaces:
– EMIFA
• NOR (8- or 16-Bit-Wide Data)
• NAND (8- or 16-Bit-Wide Data)
• 16-Bit SDRAM with 128-MB Address Space
– DDR2/Mobile DDR Memory Controller with one
of the following:
• 16-Bit DDR2 SDRAM with 256-MB Address
Space
• 16-Bit mDDR SDRAM with 256-MB Address
Space
• Three Configurable 16550-Type UART Modules:
– With Modem Control Signals
– 16-Byte FIFO
– 16x or 13x Oversampling Option
• LCD Controller
• Two Serial Peripheral Interfaces (SPIs) Each with
Multiple Chip Selects
• Two Multimedia Card (MMC)/Secure Digital (SD)
Card Interfaces with Secure Data I/O (SDIO)
Interfaces
• Two Master and Slave Inter-Integrated Circuits
( I
2
C Bus™)
• One Host-Port Interface (HPI) with 16-Bit-Wide
Muxed Address and Data Bus For High Bandwidth
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
www.ti.com
• Video Port Interface (VPIF):
– Two 8-Bit SD (BT.656), Single 16-Bit or Single
Raw (8-, 10-, and 12-Bit) Video Capture
Channels
– Two 8-Bit SD (BT.656), Single 16-Bit Video
Display Channels
• Universal Parallel Port (uPP):
– High-Speed Parallel Interface to FPGAs and
Data Converters
– Data Width on Both Channels is 8- to 16-Bit
Inclusive
– Single-Data Rate or Dual-Data Rate Transfers
– Supports Multiple Interfaces with START,
ENABLE, and WAIT Controls
• Serial ATA (SATA) Controller:
– Supports SATA I (1.5 Gbps) and SATA II
(3.0 Gbps)
– Supports all SATA Power-Management
Features
– Hardware-Assisted Native Command Queueing
(NCQ) for up to 32 Entries
– Supports Port Multiplier and Command-Based
Switching
• Real-Time Clock (RTC) with 32-kHz Oscillator and
Separate Power Rail
• Three 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
• One 64-Bit General-Purpose or Watchdog Timer
(Configurable as Two 32-Bit General-Purpose
Timers)
• Two Enhanced High-Resolution Pulse Width
Modulators (eHRPWMs):
– Dedicated 16-Bit Time-Base Counter with
Period and Frequency Control
– 6 Single-Edge Outputs, 6 Dual-Edge Symmetric
Outputs, or 3 Dual-Edge Asymmetric Outputs
– Dead-Band Generation
– PWM Chopping by High-Frequency Carrier
– Trip Zone Input
• Three 32-Bit Enhanced Capture (eCAP) Modules:
– Configurable as 3 Capture Inputs or 3 Auxiliary
Pulse Width Modulator (APWM) Outputs
– Single-Shot Capture of up to Four Event Time-
Stamps
• 361-Ball Pb-Free Plastic Ball Grid Array (PBGA)
[ZCE Suffix], 0.65-mm Ball Pitch
• 361-Ball Pb-Free PBGA [ZWT Suffix], 0.80-mm
Ball Pitch
• Commercial or Extended Temperature
1.2
•
•
•
•
Applications
•
•
•
•
Data Concentrators
Building Automation
Set Top Box
Industrial Automation
Gaming
Medical, Healthcare, Fitness
Printers
ePOS
2
AM1808 ARM Microprocessor
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Copyright © 2010–2014, Texas Instruments Incorporated
AM1808
www.ti.com
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
1.3
Description
The AM1808 ARM Microprocessor is a low-power applications processor based on ARM926EJ-S.
The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs)
to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and
high processing performance life through the maximum flexibility of a fully integrated mixed processor
solution.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and
memory system can operate continuously.
The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory
management units (MMUs) with table look-aside buffers. The ARM core processor has separate 16-KB
instruction and 16-KB data caches. Both are four-way associative with virtual index virtual tag (VIVT). The
ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.
The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management
data input/output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two inter-
integrated circuit (I
2
C Bus) interfaces; one multichannel audio serial port (McASP) with 16 serializers and
FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral
interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one
configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-
purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and
event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and
CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced
capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width
modulator (APWM) outputs; two external memory interfaces; an asynchronous and SDRAM external
memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR
controller.
The EMAC provides an efficient interface between the device and a network. The EMAC supports both
10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an
MDIO interface is available for PHY configuration. The EMAC supports the MII and RMII interfaces.
The SATA controller provides a high-speed interface to mass data storage devices. The SATA controller
supports SATA I (1.5 Gbps) and SATA II (3.0 Gbps).
The universal parallel port (uPP) provides a high-speed interface to many types of data converters,
FPGAs or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on
both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE,
and WAIT signals to provide control for a variety of data converters.
A video port interface (VPIF) is included providing a flexible video I/O port.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections in this document and
the associated peripheral reference guides.
The device has a complete set of development tools for the ARM processor. These tools include C
compilers, and scheduling, and a Windows
®
debugger interface for visibility into source code execution.
Device Information
PART NUMBER
AM1808ZCE
AM1808ZWT
PACKAGE
NFBGA (361)
NFBGA (361)
BODY SIZE
13,00 mm x 13,00 mm
16,00 mm x 16,00 mm
Copyright © 2010–2014, Texas Instruments Incorporated
AM1808 ARM Microprocessor
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3
AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
www.ti.com
1.4
Functional Block Diagram
Figure 1-1
shows the functional block diagram of the device.
JTAG Interface
System Control
Input
Clock(s)
PLL/Clock
Generator
w/OSC
General-
Purpose
Timer (x3)
RTC/
32-kHz
OSC
ARM926EJ-S CPU
With MMU
Memory
Protection
4KB ETB
16KB
16KB
I-Cache D-Cache
8KB RAM
(Vector Table)
64KB ROM
ARM Subsystem
Power/Sleep
Controller
Pin
Multiplexing
Switched Central Resource (SCR)
Peripherals
DMA
Audio Ports
Serial Interfaces
Display
Video
Parallel Port Internal Memory Customizable Interface
EDMA3
(x2)
McASP
w/FIFO
McBSP
(x2)
I
2
C
(x2)
SPI
(x2)
UART
(x3)
LCD
Ctlr
VPIF
uPP
128KB
RAM
PRU Subsystem
Control Timers
Connectivity
External Memory Interfaces
ePWM
(x2)
eCAP
(x3)
USB2.0
OTG Ctlr
PHY
USB1.1
OHCI Ctlr
PHY
EMAC
10/100 MDIO
(MII/RMII)
HPI
MMC/SD
(8b)
(x2)
SATA
EMIFA(8b/16B)
NAND/Flash
16b SDRAM
DDR2/MDDR
Controller
(1)
Note: Not all peripherals are available at the same time due to multiplexing.
Figure 1-1. Functional Block Diagram
4
AM1808 ARM Microprocessor
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Copyright © 2010–2014, Texas Instruments Incorporated
AM1808
www.ti.com
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
Table of Contents
1
AM1808 ARM Microprocessor
.........................
1
1.1
1.2
1.3
1.4
Features
..............................................
1
Applications
...........................................
2
Description
............................................
3
Functional Block Diagram
............................
4
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19
6.20
6.21
6.22
6.23
6.24
6.25
6.26
6.27
6.28
6.29
6.30
6.31
6.32
6.33
6.34
External Memory Interface A (EMIFA)
..............
98
DDR2/mDDR Memory Controller
..................
109
2
3
Revision History
.........................................
6
Device Overview
.........................................
7
3.1
3.2
3.3
3.4
3.5
Device Characteristics
................................
7
Device Compatibility
..................................
8
ARM Subsystem
......................................
8
Memory Map Summary
.............................
11
Pin Assignments
14
17
18
58
..........................
MMC / SD / SDIO (MMCSD0, MMCSD1)
.........
Serial ATA Controller (SATA)
......................
Multichannel Audio Serial Port (McASP)
..........
Multichannel Buffered Serial Port (McBSP)
........
Serial Peripheral Interface Ports (SPI0, SPI1)
.....
Inter-Integrated Circuit Serial Ports (I2C)
..........
Memory Protection Units
122
125
128
133
142
151
172
4
5
....................................
3.6
Pin Multiplexing Control
.............................
3.7
Terminal Functions
..................................
3.8
Unused Pin Configurations
..........................
Device Configuration
..................................
4.1
Boot Modes
.........................................
4.2
SYSCFG Module
....................................
4.3
Pullup/Pulldown Resistors
..........................
Specifications
...........................................
5.1
Universal Asynchronous Receiver/Transmitter
(UART)
.............................................
176
Universal Serial Bus OTG Controller (USB0)
[USB2.0 OTG]
.....................................
178
Universal Serial Bus Host Controller (USB1)
[USB1.1 OHCI]
.....................................
185
Ethernet Media Access Controller (EMAC)
........
186
Management Data Input/Output (MDIO)
...........
193
60
60
60
63
64
Absolute Maximum Ratings Over Operating
Junction Temperature Range
(Unless Otherwise Noted)
.................................
64
5.2
5.3
5.4
5.5
Handling Ratings
....................................
64
Recommended Operating Conditions
...............
65
Notes on Recommended Power-On Hours (POH)
.
67
Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Junction
Temperature (Unless Otherwise Noted)
............
68
............................
Host-Port Interface (UHPI)
.........................
Universal Parallel Port (uPP)
......................
Video Port Interface (VPIF)
........................
Enhanced Capture (eCAP) Peripheral
.............
LCD Controller (LCDC)
195
210
218
223
228
Enhanced High-Resolution Pulse-Width Modulator
(eHRPWM)
.........................................
231
Timers
..............................................
236
Real Time Clock (RTC)
............................
238
General-Purpose Input/Output (GPIO)
.............
241
Programmable Real-Time Unit Subsystem (PRUSS)
.....................................................
245
Emulation Logic
....................................
248
Device Support
.....................................
256
Documentation Support
............................
257
Community Resources
.............................
257
Trademarks
........................................
257
6
Peripheral Information and Electrical
Specifications
...........................................
69
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
Parameter Information
..............................
69
Recommended Clock and Control Signal Transition
Behavior
.............................................
70
Power Supplies
......................................
70
Reset
................................................
71
Crystal Oscillator or External Clock Input
...........
75
Clock PLLs
..........................................
76
7
Device and Documentation Support
..............
256
7.1
7.2
7.3
7.4
7.5
7.6
...................
Glossary
............................................
Electrostatic Discharge Caution
258
258
............................................
Power and Sleep Controller (PSC)
..................
EDMA
...............................................
Interrupts
8
81
87
92
Mechanical Packaging and Orderable
Information
.............................................
258
8.1
8.2
Thermal Data for ZCE Package
...................
258
Thermal Data for ZWT Package
...................
259
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Table of Contents
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