PIC18FXX20
Flash Microcontroller Programming Specification
1.0
DEVICE OVERVIEW
2.1
Hardware Requirements
This
document
includes
the
programming
specifications for the following devices:
•
•
•
•
•
•
PIC18F6520
PIC18F6620
PIC18F6720
PIC18F8520
PIC18F8620
PIC18F8720
In high voltage ICSP mode, the PIC18FXX20 requires
two programmable power supplies: one for V
DD
and
one for MCLR/V
PP
. Both supplies should have a
minimum resolution of 0.25V. Refer to Section 6.0 for
additional hardware parameters.
2.1.1
LOW VOLTAGE ICSP
PROGRAMMING
2.0
PROGRAMMING OVERVIEW
OF THE PIC18FXX20
PIC18FXX20 devices can be programmed using either
the high voltage In-Circuit Serial Programming
TM
(ICSP
TM
) method, or the low voltage ICSP method.
Both of these can be done with the device in the users’
system. The low voltage ICSP method is slightly
different than the high voltage method, and these
differences are noted where applicable. This
programming specification applies to PIC18FXX20
devices in all package types.
In low voltage ICSP mode, the PIC18FXX20 can be
programmed using a V
DD
source in the operating
range. This only means that MCLR/V
PP
does not have
to be brought to a different voltage, but can instead be
left at the normal operating voltage. Refer to
Section 6.0 for additional hardware parameters.
2.2
Pin Diagrams
The pin diagrams for the PIC18FXX20 family are
shown in Figure 2-1. The pin descriptions of these
diagrams do not represent the complete functionality of
the device types. Users should refer to the appropriate
device data sheet for complete pin descriptions.
TABLE 2-1:
Pin Name
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18FXX20
During Programming
Pin Name
Pin Type
P
P
P
P
P
I
I
I/O
Programming Enable
Power Supply
Ground
Analog Power Supply
Analog Ground
Low Voltage ICSP™ Input when LVP Configuration bit equals ‘1’
(1)
Serial Clock
Serial Data
Pin Description
MCLR/V
PP
/RA5
V
DD
(2)
V
SS
(2)
AV
DD
AV
SS
RB5
RB6
RB7
V
PP
V
DD
V
SS
AV
DD
AV
SS
PGM
SCLK
SDATA
Legend: I = Input, O = Output, P = Power
Note 1:
See Section 5.3 for more detail.
2:
All power supply and ground must be connected.
2010 Microchip Technology Inc.
DS39583C-page 1
PIC18FXX20
FIGURE 2-1:
PIC18FXX20 FAMILY PIN DIAGRAMS
RD0
V
DD
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE2
RE3
RE4
RE5
RE6
RE7
V
SS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RE1
RE0
RG0
RG1
RG2
RG3
MCLR/V
PP
RG4
V
SS
V
DD
RF7
RF6
RF5
RF4
RF3
RF2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RB0
RB1
RB2
RB3
RB4
RB5
RB6
V
SS
OSC2/RA6
OSC1
V
DD
RB7
RC5
RC4
RC3
RC2
PIC18F6520
PIC18F6620
PIC18F6720
64L TQFP
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RF1
RF0
AV
SS
RA3
RA2
RA5
RA4
RC1
AV
DD
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RH2
RH3
RE1
RE0
RG0
RG1
RG2
RG3
MCLR/V
PP
RG4
V
SS
V
DD
RF7
RF6
RF5
RF4
RF3
RF2
RH7
RH6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RJ2
RJ3
RB0
RB1
RB2
RB3
RB4
RB5
RB6
V
SS
OSC2/RA6
OSC1
V
DD
RB7
RC5
RC4
RC3
RC2
RJ7
RJ6
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Note:
Not all multiplexed pin definitions are shown. Refer to the appropriate data sheet for complete pin descriptions.
DS39583C-page 2
RH5
RH4
RF1
RF0
AV
DD
AV
SS
RA3
RA2
RA1
RA0
V
SS
V
DD
RA5
RA4
RC1
RC0
RC6
RC7
RJ4
RJ5
RH1
RH0
RE2
RE3
RE4
RE5
RE6
RE7
RD0
V
DD
V
SS
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RJ0
RJ1
RC0
RC6
RC7
RA1
RA0
V
SS
V
DD
PIC18F8520
PIC18F8620
PIC18F8720
80L TQFP
2010 Microchip Technology Inc.
PIC18FXX20
2.3
Memory Map
TABLE 2-2:
Device
PIC18F6520
PIC18F8520
PIC18F6620
PIC18F8620
PIC18F6720
PIC18F8720
The code memory space extends from 0000h to
1FFFFh (128 Kbytes) in eight 16-Kbyte blocks.
Addresses 0000h through 01FFh, however, define a
“Boot Block” region that is treated separately from
Block 1. All of these blocks define code protection
boundaries within the code memory space.
In contrast, code memory panels are defined in 8-Kbyte
boundaries. Panels are discussed in greater detail in
Section 3.2.
IMPLEMENTATION OF CODE
MEMORY
Code Memory Size (Bytes)
000000h - 007FFFh (32K)
000000h - 00FFFFh (64K)
000000h - 01FFFFh (128K)
FIGURE 2-2:
000000h
MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FXX20 DEVICES
Code Memory
01FFFFh
32 Kbytes
(PIC18FX520)
Boot Block
Unimplemented
Read as ‘0’
Block 0
Address
Range
000000h
0007FFh
000800h
001FFFh
002000h
Block 1
003FFFh
004000h
Block 2
005FFFh
006000h
1FFFFFh
Block 3
007FFFh
008000h
Block 4
013FFFh
Configuration
and ID
Space
014000h
Block 5
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
Block 6
01BFFFh
01C000h
Block 7
1FFFFFh
01FFFFh
017FFFh
018000h
Block 3
Block 3
00FFFFh
010000h
Block 2
Block 2
00BFFFh
00C000h
Block 1
Block 1
007FFFh
008000h
MEMORY SIZE / DEVICE
64 Kbytes
(PIC18FX620)
Boot Block
Block 0
128 Kbytes
(PIC18FX720)
Boot Block
Block 0
Address
Range
000000h
0001FFh
000200h
003FFFh
004000h
3FFFFFh
Note:
Sizes of memory areas not to scale.
2010 Microchip Technology Inc.
DS39583C-page 3
PIC18FXX20
In addition to the code memory space, there are three
blocks in the configuration and ID space that are
accessible to the user through Table Reads and Table
Writes. Their locations in the memory map are shown
in Figure 2-3.
Users may store identification information (ID) in eight
ID registers. These ID registers are mapped in
addresses 200000h through 200007h. The ID locations
read out normally, even after code protection is applied.
Locations 300000h through 30000Dh are reserved for
the Configuration bits. These bits select various device
options, and are described in Section 5.0. These
Configuration bits read out normally, even after code
protection.
Locations 3FFFFEh and 3FFFFFh are reserved for the
Device ID bits. These bits may be used by the
programmer to identify what device type is being
programmed, and are described in Section 5.0. These
Device ID bits read out normally, even after code
protection.
2.3.1
MEMORY ADDRESS POINTER
Memory in the address space 0000000h to 3FFFFFh is
addressed via the Table Pointer, which is comprised of
three pointer registers:
• TBLPTRU, at RAM address 0FF8h
• TBLPTRH, at RAM address 0FF7h
• TBLPTRL, at RAM address 0FF6h
TBLPTRU
Addr[21:16]
TBLPTRH
Addr[15:8]
TBLPTRL
Addr[7:0]
The 4-bit command, ‘0000’ (Core Instruction), is used
to load the Table Pointer prior to using many Read or
Write operations.
FIGURE 2-3:
000000h
CONFIGURATION AND ID LOCATIONS FOR PIC18FXX20 DEVICES
Code Memory
01FFFFh
ID Location 1
ID Location 2
ID Location 3
ID Location 4
ID Location 5
Unimplemented
Read as ‘0’
ID Location 6
ID Location 7
ID Location 8
200000h
200001h
200002h
200003h
200004h
200005h
200006h
200007h
CONFIG1L
CONFIG1H
CONFIG2L
CONFIG2H
1FFFFFh
CONFIG3L
CONFIG3H
Configuration
and ID
Space
CONFIG4L
CONFIG4H
CONFIG5L
CONFIG5H
CONFIG6L
2FFFFFh
CONFIG6H
CONFIG7L
CONFIG7H
300000h
300001h
300002h
300003h
300004h
300005h
300006h
300007h
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Device ID1
Device ID2
3FFFFFh
Note:
Sizes of memory areas are not to scale.
3FFFFEh
3FFFFFh
DS39583C-page 4
2010 Microchip Technology Inc.
PIC18FXX20
2.4
High Level Overview of the
Programming Process
FIGURE 2-4:
HIGH LEVEL
PROGRAMMING FLOW
Start
Figure 2-4 shows the high level overview of the
programming process. First, a bulk erase is performed.
Next, the Code Memory, ID Locations, and Data
EEPROM are programmed. These memories are then
verified to ensure that programming was successful. If
no errors are detected, the Configuration bits are then
programmed and verified.
Perform Bulk
Erase
Program Memory
2.5
Entering High Voltage ICSP
Program/Verify Mode
Program IDs
The high voltage ICSP Program/Verify mode is entered
by holding SCLK and SDATA low and then raising
MCLR/V
PP
to V
IHH
(high voltage). Once in this mode,
the Code Memory, Data EEPROM, ID Locations, and
Configuration bits can be accessed and programmed in
serial fashion.
The sequence that enters the device into the
Program/Verify mode places all unused I/Os in the high
impedance state.
Program Data
Verify Program
2.5.1
ENTERING LOW VOLTAGE ICSP
PROGRAM/VERIFY MODE
Verify IDs
When the LVP configuration bit is ‘1’ (see Section 5.3),
the low voltage ICSP mode is enabled. Low voltage
ICSP Program/Verify mode is entered by holding SCLK
and SDATA low, placing a logic high on PGM, and then
raising MCLR/V
PP
to V
IH
. In this mode, the RB5/PGM
pin is dedicated to the programming function and
ceases to be a general purpose I/O pin.
The sequence that enters the device into the
Program/Verify mode, places all unused I/Os in the
high impedance state.
Verify Data
Program
Configuration Bits
Verify
Configuration Bits
Done
FIGURE 2-5:
ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
P13
P1
P12
FIGURE 2-6:
ENTERING LOW
VOLTAGE PROGRAM/
VERIFY MODE
P15
V
IH
P12
MCLR/V
PP
D110
MCLR/V
PP
V
DD
V
DD
V
IH
PGM
SDATA
SCLK
SDATA = Input
SDATA
SCLK
SDATA = Input
2010 Microchip Technology Inc.
DS39583C-page 5