MT45W1MW16BDGB-708 WT TR datasheet, PDF

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MT45W1MW16BDGB-708 WT TR: DescriptionIC psram 16mbit 70ns 54vfbga; Categorystorage; File Size2MB，59 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

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MT45W1MW16BDGB-708 WT TR Overview

IC psram 16mbit 70ns 54vfbga

MT45W1MW16BDGB-708 WT TR Parametric

Parameter Name	Attribute value
Datasheets
MT45W1MW16BDGB
Product Photos
54 VFBGA Package
Standard Package	1,000
Category	Integrated Circuits (ICs)
Family	Memory
Packaging	Tape & Reel (TR)
Format - Memory	RAM
Memory Type	PSRAM (Page)
Memory Size	16M (1M x 16)
Speed	70ns
Interface	Parallel
Voltage - Supply	1.7 V ~ 1.95 V
Operating Temperature	-30°C ~ 85°C
Package / Case	54-VFBGA
Supplier Device Package	54-VFBGA (6x8)
Other Names	557-1274-2MT45W1MW16BDGB-708 WT TR-ND

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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Features

Async/Page/Burst CellularRAM™ Memory

MT45W1MW16BDGB

Features

• Single device supports asynchronous, page, and

burst operations

• Random access time: 70ns

• V

, V

Q voltages:

–

1.7–1.95V V

–

1.7–3.6V

• Page mode read access

–

Sixteen-word page size

–

Interpage read access: 70ns

–

Intrapage read access: 20ns

• Burst mode write access: continuous burst

• Burst mode read access:

–

4, 8, or 16 words, or continuous burst

–

MAX clock rate: 104 MHz (

CLK = 9.62ns)

–

Burst initial latency: 39ns (4 clocks) @ 104 MHz

–

ACLK: 7ns @ 104 MHz

• Low power consumption

–

Asynchronous read: <20mA

–

Intrapage read: <15mA

–

Intrapage read initial access, burst read:

–

(39ns [4 clocks] @ 104 MHz) < 35mA

–

Continuous burst read: <28mA

–

Standby: 70µA

–

Deep power-down: <10µA (TYP @ 25°C)

• Low-power features

–

Temperature-compensated refresh (TCR)

–

On-chip temperature sensor

–

Partial-array refresh (PAR)

–

Deep power-down (DPD) mode

Figure 1:

54-Ball VFBGA

LB#

OE#

CRE

DQ8

UB#

CE#

DQ0

DQ9

DQ10

DQ1

DQ2

DQ11

A17

DQ3

DQ12

A16

DQ4

DQ14

DQ13

A14

A15

DQ5

DQ6

DQ15

A19

A12

A13

WE#

DQ7

A18

A10

A11

WAIT

CLK

ADV#

Top View

(Ball Down)

Options (continued)

• Standby power

–

Standard

• Operating temperature range

–

Wireless (–30°C to +85°C)

–

Industrial (–40°C to +85°C)

Designator

None

Options

• Configuration

–

1 Meg x 16

• Package

–

54-ball VFBGA (“green”)

• Access time

–

70ns access

• Frequency

–

80 MHz

–

104 MHz

Designator

MT45W1MW16BD

-70

Notes: 1. 3.6V I/O and –30°C exceed the CellularRAM

Workgroup 1.0 specifications.

2. Contact factory.

Part Number Example:

MT45W1MW16BDGB-701WT

PDF: 09005aef81cb58ed/Source: 09005aef81c7a667

16mb_burst_cr1_0_p23z_1.fm - Rev. H 4/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Burst Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

WAIT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Temperature-Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Partial-Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Deep Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Access Using CRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Software Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Burst Length (BCR[2:0]) Default = Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Burst Wrap (BCR[3]) Default = Burst No Wrap (Within Burst Length) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid . . . . . . . . .25

WAIT Polarity (BCR[10]) Default = WAIT Active HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Latency Counter (BCR[13:11]) Default = Three-Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Operating Mode (BCR[15]) Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Deep Power-Down (RCR[4]) Default = DPD Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Temperature-Compensated Refresh (RCR[6:5]) Default = On-Chip Temperature Sensor. . . . . . . . . . . . . . . .28

Page Mode Operation (RCR[7]) Default = Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Maximum and Typical Standby Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

PDF: 09005aef81cb58ed/Source: 09005aef81c7a667

16mb_burst_cr1_0_p23zTOC.fm - Rev. H 4/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

List of Figures

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Figure 5:

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Figure 8:

Figure 9:

Figure 10:

Figure 11:

Figure 12:

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Figure 17:

Figure 18:

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Figure 21:

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Figure 25:

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Figure 27:

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Figure 36:

Figure 37:

Figure 38:

Figure 39:

Figure 40:

Figure 41:

Figure 42:

Figure 43:

Figure 44:

Figure 45:

Figure 46:

Figure 47:

54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Functional Block Diagram – 1 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Power-Up Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

WRITE Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Page Mode READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Burst Mode READ (4-word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Burst Mode WRITE (4-word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Wired-OR WAIT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Refresh Collision During READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Refresh Collision During WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Configuration Register WRITE in Asynchronous Mode Followed by READ ARRAY Operation . . . .19

Configuration Register WRITE in Synchronous Mode Followed by READ ARRAY Operation . . . . .20

Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

WAIT Configuration (BCR[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

WAIT Configuration (BCR[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

WAIT Configuration During Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Latency Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Refresh Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Typical Refresh Current vs. Temperature (I

TCR

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Asynchronous READ Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Page Mode READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Single-Access Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

4-Word Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

READ Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition . .43

CE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

LB#/UB#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

WE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Burst WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition .49

Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Asynchronous WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Asynchronous WRITE Followed by Burst READ – ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Burst READ Followed by Asynchronous WRITE (WE#-Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Burst READ Followed by Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Asynchronous WRITE Followed by Asynchronous READ – ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . .55

Asynchronous WRITE Followed by Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

PDF: 09005aef81cb58ed/Source: 09005aef81c7a667

16mb_burst_cr1_0_p23zLOF.fm - Rev. H 4/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

List of Tables

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Table 11:

Table 12:

Table 13:

Table 14:

Table 15:

Table 16:

VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Bus Operations – Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Bus Operations – Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Latency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

16Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Maximum Standby Currents for Applying PAR and TCR Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Asynchronous READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Burst READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Asynchronous WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Burst WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

PDF: 09005aef81cb58ed/Source: 09005aef81c7a667

16mb_burst_cr1_0_p23zLOT.fm - Rev. H 4/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory

General Description

Micron

CellularRAM™ is a high-speed, CMOS PSRAM memory device developed for

low-power, portable applications. The MT45W1MW16BDGB is a 16Mb DRAM core

device organized as 1 Meg x 16 bits. This device includes an industry-standard

burst mode Flash interface that dramatically increases read/write bandwidth compared

with other low-power SRAM or Pseudo SRAM offerings.

For seamless operation on a burst Flash bus, CellularRAM products incorporate a trans-

parent self-refresh mechanism. The hidden refresh requires no additional support from

the system memory controller and has no significant impact on device read/write

performance.

Two user-accessible control registers define device operation. The bus configuration

bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh

configuration register (RCR) is used to control how refresh is performed on the DRAM

array. These registers are automatically loaded with default settings during power-up

and can be updated anytime during normal operation.

Special attention has been focused on standby current consumption during self refresh.

CellularRAM products include three system-accessible mechanisms to minimize

standby current. Partial-array refresh (PAR) limits refresh to only that part of the DRAM

array that contains essential data. Temperature-compensated refresh (TCR) uses an on-

chip sensor to adjust the refresh rate to match the device temperature. The refresh rate

decreases at lower temperatures to minimize current consumption during standby. TCR

can also be set by the system for maximum device temperatures of +85°C, +45°C, and

+15°C. Deep power-down (DPD) halts the REFRESH operation altogether and is used

when no vital information is stored in the device. These three refresh mechanisms are

accessed through the RCR.

PDF: 09005aef81cb58ed/Source: 09005aef81c7a667

16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT45W1MW16BDGB-708 WT TR Related Products

	MT45W1MW16BDGB-708 WT TR	MT45W1MW16BDGB-701 IT TR	MT45W1MW16BDGB-701 IT	MT45W1MW16BDGB-708 AT	MT45W1MW16BDGB-701 WT TR	MT45W1MW16BDGB-708 AT TR
Description	IC psram 16mbit 70ns 54vfbga	IC psram 16mbit 70ns 54vfbga	IC psram 16mbit 70ns 54vfbga	IC psram 16mbit 70ns 54vfbga	IC psram 16mbit 70ns 54vfbga	IC psram 16mbit 70ns 54vfbga
Standard Package	1,000	1	1,000	1,000	1,000	-
Category	Integrated Circuits (ICs)	Integrated Circuits (ICs)	Integrated Circuits (ICs)	Integrated Circuits (ICs)	Integrated Circuits (ICs)	-
Family	Memory	Memory	Memory	Memory	Memory	-
Packaging	Tape & Reel (TR)	Cut Tape (CT)	Tray	Tray	Tape & Reel (TR)	-
Format - Memory	RAM	RAM	RAM	RAM	RAM	-
Memory Type	PSRAM (Page)	PSRAM (Page)	PSRAM (Page)	PSRAM (Page)	PSRAM (Page)	-
Memory Size	16M (1M x 16)	16M (1M x 16)	16M (1M x 16)	16M (1M x 16)	16M (1M x 16)	-
Speed	70ns	70ns	70ns	70ns	70ns	-
Interface	Parallel	Parallel	Parallel	Parallel	Parallel	-
Voltage - Supply	1.7 V ~ 1.95 V	1.7 V ~ 1.95 V	1.7 V ~ 1.95 V	1.7 V ~ 1.95 V	1.7 V ~ 1.95 V	-
Operating Temperature	-30°C ~ 85°C	-40°C ~ 85°C	-40°C ~ 85°C	-40°C ~ 105°C	-30°C ~ 85°C	-
Package / Case	54-VFBGA	54-VFBGA	54-VFBGA	54-VFBGA	54-VFBGA	-
Supplier Device Package	54-VFBGA (6x8)	54-VFBGA (6x8)	54-VFBGA (6x8)	54-VFBGA (6x8)	54-VFBGA (6x8)	-

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