MKL17Z256VFT4 datasheet, PDF - EEWORLD Datasheet

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MKL17Z256VFT4: DescriptionIC mcu 32bit 256k flash 48qfn; Categorysemiconductor The embedded processor and controller; File Size5MB，865 Pages; ManufacturerFREESCALE (NXP); Environmental Compliance

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IC mcu 32bit 256k flash 48qfn

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Datasheets
KL17 Sub-Family Ref Manual
Standard Package	490
Category	Integrated Circuits (ICs)
Family	Embedded - Microcontrollers
Packaging	*
Core Process	ARM® Cortex®-M0+
Core Size	32-Bi
Speed	48MHz
Connectivity	I²C, LIN, SPI, UART/USART
Peripherals	Brown-out Detect/Reset, DMA, I²S, LVD, POR, PWM, WDT
Number of I/O	-
Program Memory Size	256KB (256K x 8)
Program Memory Type	FLASH
EEPROM Size	-
RAM Size	32K x 8
Voltage - Supply (Vcc/Vdd)	1.71 V ~ 3.6 V
Data Converters	A/D 18x16b, D/A 1x12b
Oscillator Type	Internal
Operating Temperature	-40°C ~ 105°C
Package / Case	*
Supplier Device Package	*

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KL17 Sub-Family Reference Manual

Supports: MKL17Z128VFM4, MKL17Z256VFM4, MKL17Z128VFT4,

MKL17Z256VFT4, MKL17Z128VMP4, MKL17Z256VMP4,

MKL17Z128VLH4, MKL17Z256VLH4

Document Number: KL17P64M48SF6RM

Rev 4, September 2014

Contents

Section number

Title

Chapter 1

About This Document

1.1

Overview.......................................................................................................................................................................35

1.1.1

1.1.2

1.2

Purpose...........................................................................................................................................................35

Audience........................................................................................................................................................ 35

Page

Conventions.................................................................................................................................................................. 35

1.2.1

1.2.2

1.2.3

Numbering systems........................................................................................................................................35

Typographic notation..................................................................................................................................... 36

Special terms.................................................................................................................................................. 36

Chapter 2

Introduction

2.1

Overview.......................................................................................................................................................................37

2.1.1

2.2

Sub-family introduction................................................................................................................................. 37

Module functional categories........................................................................................................................................38

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

2.2.7

2.2.8

2.2.9

ARM Cortex-M0+ core modules................................................................................................................... 38

System modules............................................................................................................................................. 39

Memories and memory interfaces..................................................................................................................40

Clocks.............................................................................................................................................................40

Security and integrity modules...................................................................................................................... 41

Analog modules............................................................................................................................................. 41

Timer modules............................................................................................................................................... 41

Communication interfaces............................................................................................................................. 42

Human-machine interfaces............................................................................................................................ 42

2.3

Module to module interconnects...................................................................................................................................43

2.3.1

2.3.2

Interconnection overview...............................................................................................................................43

Analog reference options............................................................................................................................... 45

KL17 Sub-Family Reference Manual , Rev. 4, September 2014

Freescale Semiconductor, Inc.

Section number

Title

Chapter 3

Core Overview

Page

3.1

ARM Cortex-M0+ core introduction............................................................................................................................ 47

3.1.1

3.1.2

3.1.3

3.1.4

Buses, interconnects, and interfaces.............................................................................................................. 47

System tick timer........................................................................................................................................... 47

Debug facilities.............................................................................................................................................. 47

Core privilege levels...................................................................................................................................... 48

3.2

Nested vectored interrupt controller (NVIC) ...............................................................................................................48

3.2.1

3.2.2

3.2.3

Interrupt priority levels.................................................................................................................................. 48

Non-maskable interrupt..................................................................................................................................48

Interrupt channel assignments........................................................................................................................48

3.3

AWIC introduction....................................................................................................................................................... 51

3.3.1

Wake-up sources............................................................................................................................................ 51

Chapter 4

Memory Map

4.1

Flash memory............................................................................................................................................................... 53

4.1.1

4.1.2

4.1.3

4.1.4

4.1.5

4.2

Flash memory map.........................................................................................................................................53

Flash security................................................................................................................................................. 54

Flash modes....................................................................................................................................................54

Erase all flash contents...................................................................................................................................54

FTFA_FOPT register..................................................................................................................................... 54

SRAM........................................................................................................................................................................... 55

4.2.1

4.2.2

4.2.3

SRAM sizes....................................................................................................................................................55

SRAM ranges................................................................................................................................................. 55

SRAM retention in low power modes............................................................................................................56

4.3

4.4

4.5

4.6

System Register file...................................................................................................................................................... 56

Introduction...................................................................................................................................................................57

System memory map.....................................................................................................................................................57

Bit Manipulation Engine...............................................................................................................................................58

KL17 Sub-Family Reference Manual , Rev. 4, September 2014

Freescale Semiconductor, Inc.

Section number

4.7

Title

Page

Peripheral bridge (AIPS-Lite) memory map.................................................................................................................58

4.7.1

4.7.2

Read-after-write sequence and required serialization of memory operations................................................58

Peripheral bridge (AIPS-Lite) memory map..................................................................................................59

Chapter 5

Clock Distribution

5.1

5.2

5.3

5.4

Introduction...................................................................................................................................................................63

Programming model......................................................................................................................................................63

High-level device clocking diagram............................................................................................................................. 63

Clock definitions...........................................................................................................................................................64

5.4.1

5.5

Device clock summary...................................................................................................................................65

Internal clocking requirements..................................................................................................................................... 67

5.5.1

5.5.2

Clock divider values after reset......................................................................................................................68

VLPR mode clocking.....................................................................................................................................68

5.6

5.7

Clock gating.................................................................................................................................................................. 68

Module clocks...............................................................................................................................................................69

5.7.1

5.7.2

5.7.3

5.7.4

5.7.5

5.7.6

5.7.7

5.7.8

5.7.9

PMC 1-kHz LPO clock.................................................................................................................................. 70

COP clocking................................................................................................................................................. 70

RTC clocking................................................................................................................................................. 71

RTC_CLKOUT and CLKOUT32K clocking................................................................................................ 71

LPTMR clocking............................................................................................................................................72

TPM clocking.................................................................................................................................................73

LPUART clocking......................................................................................................................................... 73

FlexIO clocking..............................................................................................................................................74

I2S/SAI clocking............................................................................................................................................75

Chapter 6

Reset and Boot

6.1

6.2

Introduction...................................................................................................................................................................77

Reset..............................................................................................................................................................................77

6.2.1

Power-on reset (POR).................................................................................................................................... 78

KL17 Sub-Family Reference Manual , Rev. 4, September 2014

Freescale Semiconductor, Inc.

MKL17Z256VFT4 Related Products

	MKL17Z256VFT4	MKL17Z256VFM4	MKL17Z256VMP4	MKL17Z256VLH4
Description	IC mcu 32bit 256k flash 48qfn	IC mcu 32bit 256k flash 32qfn	IC mcu 32bit 256k flash 64mapbga	IC mcu 32bit 256k flash 64qfn

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